366 lines
18 KiB
Verilog
366 lines
18 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache #(
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// Size of cache in bytes
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parameter CACHE_SIZE = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE = 16,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Forward SNP Queue
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parameter FFSQ_SIZE = 8,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Enable dram update
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parameter DRAM_ENABLE = 1,
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// Enable snoop forwarding
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parameter SNOOP_FORWARDING = 0,
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// Prefetcher
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parameter PRFQ_SIZE = 64,
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parameter PRFQ_STRIDE = 0,
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// core request tag size
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parameter CORE_TAG_WIDTH = 1,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = 0,
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// dram request tag size
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parameter DRAM_TAG_WIDTH = 1
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) (
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input wire clk,
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input wire reset,
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// Core request
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input wire [NUM_REQUESTS-1:0] core_req_valid,
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input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_read,
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input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_write,
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input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
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input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
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input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
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output wire core_req_ready,
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// Core response
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output wire [NUM_REQUESTS-1:0] core_rsp_valid,
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output wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
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output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
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input wire core_rsp_ready,
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// DRAM request
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output wire dram_req_read,
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output wire dram_req_write,
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output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
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output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
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input wire dram_req_ready,
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// DRAM response
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input wire dram_rsp_valid,
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input wire [`BANK_LINE_WIDTH-1:0] dram_rsp_data,
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input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
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output wire dram_rsp_ready,
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// Snoop Req
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input wire snp_req_valid,
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input wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr,
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output wire snp_req_ready,
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// Snoop Forward
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output wire snp_fwd_valid,
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output wire [`DRAM_ADDR_WIDTH-1:0] snp_fwd_addr,
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input wire snp_fwd_ready
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);
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wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_pop;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
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wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid;
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wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data;
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wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag;
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wire dfqq_full;
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wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid;
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wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_fill_req_addr;
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wire [NUM_BANKS-1:0] per_bank_dram_fill_rsp_ready;
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wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop;
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wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid;
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wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr;
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wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] per_bank_dram_wb_req_data;
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wire [NUM_BANKS-1:0] per_bank_reqq_full;
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wire [NUM_BANKS-1:0] per_bank_snp_req_full;
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wire [NUM_BANKS-1:0] per_bank_snp_fwd_valid;
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wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_snp_fwd_addr;
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wire [NUM_BANKS-1:0] per_bank_snp_fwd_pop;
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`DEBUG_BEGIN
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wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp;
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`DEBUG_END
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assign dram_req_tag = dram_req_addr;
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assign core_req_ready = ~(| per_bank_reqq_full);
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assign snp_req_ready = ~(| per_bank_snp_req_full);
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assign dram_rsp_ready = (| per_bank_dram_fill_rsp_ready);
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VX_cache_core_req_bank_sel #(
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS)
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) cache_core_req_bank_sell (
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.core_req_valid (core_req_valid),
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.core_req_addr (core_req_addr),
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.per_bank_valids (per_bank_valids)
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);
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genvar i;
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generate
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for (i = 0; i < NUM_BANKS; i = i + 1) begin
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wire [NUM_REQUESTS-1:0] curr_bank_core_req_valids;
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wire [NUM_REQUESTS-1:0][31:0] curr_bank_core_req_addr;
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wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
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wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data;
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wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] curr_bank_core_req_read;
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wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] curr_bank_core_req_write;
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wire curr_bank_core_rsp_pop;
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wire curr_bank_core_rsp_valid;
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wire [`REQS_BITS-1:0] curr_bank_core_rsp_tid;
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wire [`WORD_WIDTH-1:0] curr_bank_core_rsp_data;
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wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag;
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wire curr_bank_dram_fill_rsp_valid;
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wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] curr_bank_dram_fill_rsp_data;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_rsp_addr;
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wire curr_bank_dram_fill_rsp_ready;
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wire curr_bank_dram_fill_req_full;
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wire curr_bank_dram_fill_req_valid;
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wire curr_bank_dram_fill_req_is_snp;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_req_addr;
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wire curr_bank_dram_wb_req_pop;
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wire curr_bank_dram_wb_req_valid;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_wb_req_addr;
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wire[`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] curr_bank_dram_wb_req_data;
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wire curr_bank_snp_req_valid;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_req_addr;
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wire curr_bank_snp_req_full;
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wire curr_bank_snp_fwd_valid;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_fwd_addr;
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wire curr_bank_snp_fwd_pop;
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wire curr_bank_reqq_full;
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// Core Req
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assign curr_bank_core_req_valids = per_bank_valids[i];
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assign curr_bank_core_req_addr = core_req_addr;
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assign curr_bank_core_req_data = core_req_data;
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assign curr_bank_core_req_tag = core_req_tag;
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assign curr_bank_core_req_read = core_req_read;
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assign curr_bank_core_req_write = core_req_write;
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assign per_bank_reqq_full[i] = curr_bank_reqq_full;
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// Core WB
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assign curr_bank_core_rsp_pop = per_bank_core_rsp_pop[i];
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assign per_bank_core_rsp_valid [i] = curr_bank_core_rsp_valid;
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assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid;
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assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag;
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assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data;
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// Dram fill request
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assign curr_bank_dram_fill_req_full = dfqq_full;
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assign per_bank_dram_fill_req_valid[i] = curr_bank_dram_fill_req_valid;
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assign per_bank_dram_fill_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_fill_req_addr, i);
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assign per_bank_dram_fill_req_is_snp[i] = curr_bank_dram_fill_req_is_snp;
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// Dram fill response
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assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid && (`DRAM_ADDR_BANK(dram_rsp_tag) == i);
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assign curr_bank_dram_fill_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag);
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assign curr_bank_dram_fill_rsp_data = dram_rsp_data;
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assign per_bank_dram_fill_rsp_ready[i] = curr_bank_dram_fill_rsp_ready;
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// Dram writeback request
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assign curr_bank_dram_wb_req_pop = per_bank_dram_wb_queue_pop[i];
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assign per_bank_dram_wb_req_valid[i] = curr_bank_dram_wb_req_valid;
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assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i);
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assign per_bank_dram_wb_req_data[i] = curr_bank_dram_wb_req_data;
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// Snoop Request
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assign curr_bank_snp_req_valid = snp_req_valid && (`DRAM_ADDR_BANK(snp_req_addr) == i);
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assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr);
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assign per_bank_snp_req_full[i] = curr_bank_snp_req_full;
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// Snoop Fwd
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assign per_bank_snp_fwd_valid[i] = curr_bank_snp_fwd_valid;
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assign per_bank_snp_fwd_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_snp_fwd_addr, i);
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assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[i];
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VX_bank #(
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.CACHE_SIZE (CACHE_SIZE),
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FFSQ_SIZE (FFSQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.DRAM_ENABLE (DRAM_ENABLE),
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.WRITE_ENABLE (WRITE_ENABLE),
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.SNOOP_FORWARDING (SNOOP_FORWARDING),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
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) bank (
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valids (curr_bank_core_req_valids),
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.core_req_read (curr_bank_core_req_read),
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.core_req_write (curr_bank_core_req_write),
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.core_req_addr (curr_bank_core_req_addr),
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.core_req_data (curr_bank_core_req_data),
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.core_req_tag (curr_bank_core_req_tag),
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.core_req_full (curr_bank_reqq_full),
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.core_req_ready (core_req_ready),
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// Core response
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.core_rsp_valid (curr_bank_core_rsp_valid),
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.core_rsp_tid (curr_bank_core_rsp_tid),
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.core_rsp_data (curr_bank_core_rsp_data),
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.core_rsp_tag (curr_bank_core_rsp_tag),
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.core_rsp_pop (curr_bank_core_rsp_pop),
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// Dram fill request
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.dram_fill_req_valid (curr_bank_dram_fill_req_valid),
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.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
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.dram_fill_req_is_snp (curr_bank_dram_fill_req_is_snp),
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.dram_fill_req_full (curr_bank_dram_fill_req_full),
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// Dram fill response
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.dram_fill_rsp_valid (curr_bank_dram_fill_rsp_valid),
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.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
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.dram_fill_rsp_addr (curr_bank_dram_fill_rsp_addr),
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.dram_fill_rsp_ready (curr_bank_dram_fill_rsp_ready),
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// Dram writeback request
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.dram_wb_req_valid (curr_bank_dram_wb_req_valid),
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.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
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.dram_wb_req_data (curr_bank_dram_wb_req_data),
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.dram_wb_req_pop (curr_bank_dram_wb_req_pop),
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// Snoop request
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.snp_req_valid (curr_bank_snp_req_valid),
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.snp_req_addr (curr_bank_snp_req_addr),
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.snp_req_full (curr_bank_snp_req_full),
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// Snoop forwarding
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.snp_fwd_valid (curr_bank_snp_fwd_valid),
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.snp_fwd_addr (curr_bank_snp_fwd_addr),
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.snp_fwd_pop (curr_bank_snp_fwd_pop)
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);
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end
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endgenerate
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VX_cache_core_rsp_merge #(
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
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) cache_core_rsp_merge (
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.per_bank_core_rsp_tid (per_bank_core_rsp_tid),
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.per_bank_core_rsp_valid (per_bank_core_rsp_valid),
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.per_bank_core_rsp_data (per_bank_core_rsp_data),
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.per_bank_core_rsp_tag (per_bank_core_rsp_tag),
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.per_bank_core_rsp_pop (per_bank_core_rsp_pop),
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.core_rsp_valid (core_rsp_valid),
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.core_rsp_data (core_rsp_data),
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.core_rsp_tag (core_rsp_tag),
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.core_rsp_ready (core_rsp_ready)
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);
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VX_cache_dram_req_arb #(
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.PRFQ_SIZE (PRFQ_SIZE),
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.PRFQ_STRIDE (PRFQ_STRIDE)
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) cache_dram_req_arb (
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.clk (clk),
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.reset (reset),
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.dfqq_full (dfqq_full),
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.per_bank_dram_fill_req_valid (per_bank_dram_fill_req_valid),
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.per_bank_dram_fill_req_addr (per_bank_dram_fill_req_addr),
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.per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop),
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.per_bank_dram_wb_req_valid (per_bank_dram_wb_req_valid),
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.per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr),
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.per_bank_dram_wb_req_data (per_bank_dram_wb_req_data),
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.dram_req_read (dram_req_read),
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.dram_req_write (dram_req_write),
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.dram_req_addr (dram_req_addr),
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.dram_req_data (dram_req_data),
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.dram_req_ready (dram_req_ready)
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);
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VX_snp_fwd_arb #(
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.NUM_BANKS(NUM_BANKS),
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.BANK_LINE_SIZE(BANK_LINE_SIZE)
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) snp_fwd_arb (
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.per_bank_snp_fwd_valid (per_bank_snp_fwd_valid),
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.per_bank_snp_fwd_addr (per_bank_snp_fwd_addr),
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.per_bank_snp_fwd_pop (per_bank_snp_fwd_pop),
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.snp_fwd_valid (snp_fwd_valid),
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.snp_fwd_addr (snp_fwd_addr),
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.snp_fwd_ready (snp_fwd_ready)
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);
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endmodule |