89 lines
3.4 KiB
Verilog
89 lines
3.4 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache_dfq_queue #(
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 0,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 0,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 0
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) (
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input wire clk,
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input wire reset,
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input wire dfqq_push,
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input wire[NUM_BANKS-1:0] per_bank_dram_fill_req_valid,
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input wire[NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_fill_req_addr,
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input wire dfqq_pop,
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output wire dfqq_req,
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output wire[`DRAM_ADDR_WIDTH-1:0] dfqq_req_addr,
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output wire dfqq_empty,
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output wire dfqq_full
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);
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wire[NUM_BANKS-1:0] out_per_bank_dram_fill_req_valid;
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wire[NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] out_per_bank_dram_fill_req_addr;
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reg [NUM_BANKS-1:0] use_per_bank_dram_fill_req_valid;
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reg [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] use_per_bank_dram_fill_req_addr;
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wire[NUM_BANKS-1:0] use_per_bqual_bank_dram_fill_req_valid;
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wire[NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] qual_bank_dram_fill_req_addr;
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wire[NUM_BANKS-1:0] updated_bank_dram_fill_req_valid;
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wire o_empty;
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wire use_empty = !(| use_per_bank_dram_fill_req_valid);
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wire out_empty = !(| out_per_bank_dram_fill_req_valid) || o_empty;
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wire push_qual = dfqq_push && !dfqq_full;
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wire pop_qual = dfqq_pop && use_empty && !out_empty;
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VX_generic_queue #(
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.DATAW(NUM_BANKS * (1+`DRAM_ADDR_WIDTH)),
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.SIZE(DFQQ_SIZE)
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) dfqq_queue (
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.clk (clk),
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.reset (reset),
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.push (push_qual),
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.data_in ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}),
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.pop (pop_qual),
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.data_out({out_per_bank_dram_fill_req_valid, out_per_bank_dram_fill_req_addr}),
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.empty (o_empty),
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.full (dfqq_full)
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);
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assign use_per_bqual_bank_dram_fill_req_valid = use_empty ? (out_per_bank_dram_fill_req_valid & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req_valid & {NUM_BANKS{!use_empty}});
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assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr;
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wire[`BANK_BITS-1:0] qual_request_index;
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wire qual_has_request;
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VX_generic_priority_encoder #(
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.N(NUM_BANKS)
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) sel_bank (
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.valids(use_per_bqual_bank_dram_fill_req_valid),
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.index (qual_request_index),
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.found (qual_has_request)
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);
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assign dfqq_empty = !qual_has_request;
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assign dfqq_req = use_per_bqual_bank_dram_fill_req_valid [qual_request_index];
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assign dfqq_req_addr = qual_bank_dram_fill_req_addr[qual_request_index];
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assign updated_bank_dram_fill_req_valid = use_per_bqual_bank_dram_fill_req_valid & (~(1 << qual_request_index));
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always @(posedge clk) begin
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if (reset) begin
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use_per_bank_dram_fill_req_valid <= 0;
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use_per_bank_dram_fill_req_addr <= 0;
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end else begin
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if (dfqq_pop && qual_has_request) begin
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use_per_bank_dram_fill_req_valid <= updated_bank_dram_fill_req_valid;
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use_per_bank_dram_fill_req_addr <= qual_bank_dram_fill_req_addr;
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end
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end
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end
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endmodule |