186 lines
3.9 KiB
Verilog
186 lines
3.9 KiB
Verilog
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`include "VX_define.v"
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module VX_fetch (
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input wire clk,
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input wire reset,
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input wire in_branch_dir,
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input wire in_freeze,
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input wire[31:0] in_branch_dest,
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input wire in_branch_stall,
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input wire in_fwd_stall,
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input wire in_branch_stall_exe,
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input wire in_jal,
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input wire[31:0] in_jal_dest,
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input wire in_interrupt,
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input wire in_debug,
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input wire[31:0] in_instruction,
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output wire[31:0] out_instruction,
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output wire out_delay,
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output wire[31:0] out_curr_PC,
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output wire out_valid[`NT_M1:0]
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);
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reg stall_reg;
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reg delay_reg;
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reg[31:0] old;
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reg[4:0] state;
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reg[31:0] real_PC;
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reg[31:0] JAL_reg;
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reg[31:0] BR_reg;
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reg prev_debug;
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reg delay;
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reg[31:0] PC_to_use;
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reg[31:0] PC_to_use_temp;
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reg stall;
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reg[31:0] temp_PC;
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reg[31:0] out_PC;
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reg[4:0] temp_state;
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reg[4:0] tempp_state;
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reg[`NT_M1:0] valid;
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// integer ini_cur_th = 0;
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genvar out_cur_th;
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initial begin
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// for (ini_cur_th = 0; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
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// valid[ini_cur_th] = 1; // Thread 1 active
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valid[0] = 1;
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// valid[1] = 0;
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stall_reg = 0;
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delay_reg = 0;
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old = 0;
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state = 0;
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real_PC = 0;
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JAL_reg = 0;
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BR_reg = 0;
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prev_debug = 0;
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end
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always @(*) begin
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case(state)
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5'h00: PC_to_use_temp = real_PC;
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5'h01: PC_to_use_temp = JAL_reg;
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5'h02: PC_to_use_temp = BR_reg;
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5'h03: PC_to_use_temp = real_PC;
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5'h04: PC_to_use_temp = old;
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default: PC_to_use_temp = 32'h0;
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endcase // state
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end
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assign out_delay = 0;
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assign delay = out_delay;
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always @(*) begin
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if ((delay_reg == 1'b1) && (in_freeze == 1'b0)) begin
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// $display("Using old cuz delay: PC: %h",old);
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PC_to_use = old;
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end else if (in_debug == 1'b1) begin
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if (prev_debug == 1'b1) begin
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PC_to_use = old;
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end else begin
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PC_to_use = real_PC;
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end
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end else if (stall_reg == 1'b1) begin
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// $display("Using old cuz stall: PC: %h\treal_pc: %h",old, real_PC);
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PC_to_use = old;
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end else begin
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PC_to_use = PC_to_use_temp;
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end
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end
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assign stall = in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || delay || in_freeze;
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assign out_instruction = stall ? 32'b0 : in_instruction;
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generate
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for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1)
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assign out_valid[out_cur_th] = stall ? 1'b0 : valid[out_cur_th];
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endgenerate
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always @(*) begin
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if ((in_jal == 1'b1) && (delay_reg == 1'b0)) begin
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temp_PC = in_jal_dest;
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end else if ((in_branch_dir == 1'b1) && (delay_reg == 1'b0)) begin
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temp_PC = in_branch_dest;
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end else begin
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temp_PC = PC_to_use;
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end
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end
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assign out_PC = temp_PC;
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always @(*) begin
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if (in_jal == 1'b1) begin
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temp_state = 5'h1;
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end else if (in_branch_dir == 1'b1) begin
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temp_state = 5'h2;
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end else begin
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temp_state = 5'h0;
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end
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end
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assign tempp_state = in_interrupt ? 5'h3 : temp_state;
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assign out_curr_PC = out_PC;
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always @(posedge clk or posedge reset) begin
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if(reset) begin
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state <= 0;
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stall_reg <= 0;
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delay_reg <= 0;
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old <= 0;
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real_PC <= 0;
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JAL_reg <= 0;
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BR_reg <= 0;
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prev_debug <= 0;
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end else begin
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if (in_debug == 1'b1) begin
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state <= 5'h3;
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end else begin
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if (prev_debug == 1'b1) begin
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state <= 5'h4;
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end else begin
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state <= tempp_state;
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end
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end
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stall_reg <= stall;
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delay_reg <= delay || in_freeze;
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old <= out_PC;
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real_PC <= PC_to_use + 32'h4;
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JAL_reg <= in_jal_dest + 32'h4;
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BR_reg <= in_branch_dest + 32'h4;
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prev_debug <= in_debug;
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end
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end
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// always @(*) begin
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// $display("Fetch out pc: %h", out_PC);
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// end
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endmodule |