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d3d82de29ea92c4f59a48e416394fe8fab4ce966
kernels/hw/rtl/cache
History
Blaise Tine d3d82de29e minor update
2021-08-26 09:49:57 -07:00
..
VX_bank.v
fixed Verilator warnings
2021-08-13 05:52:43 -04:00
VX_cache_define.vh
MSHR Redesign: removed fifo replay constraints and overheads
2021-08-12 01:49:32 -07:00
VX_cache.v
LKG Build (reset network update -fmax=236 mhz 4c)
2021-08-23 01:59:22 -07:00
VX_core_req_bank_sel.v
minor update
2021-08-26 09:49:57 -07:00
VX_core_rsp_merge.v
dcache response bus optimization
2021-07-12 10:14:48 -07:00
VX_data_access.v
block ram refactoring (multi-porting supporting and simulation support)
2021-08-26 08:19:44 -07:00
VX_flush_ctrl.v
refactoring cache_config
2021-05-27 14:41:46 -07:00
VX_miss_resrv.v
block ram refactoring (multi-porting supporting and simulation support)
2021-08-26 08:19:44 -07:00
VX_nc_bypass.v
using lzc instead of priority encoder
2021-08-26 08:05:54 -07:00
VX_shared_mem.v
block ram refactoring (multi-porting supporting and simulation support)
2021-08-26 08:19:44 -07:00
VX_tag_access.v
block ram refactoring (multi-porting supporting and simulation support)
2021-08-26 08:19:44 -07:00
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