105 lines
5.8 KiB
Verilog
105 lines
5.8 KiB
Verilog
`include "VX_define.vh"
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module VX_writeback #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_commit_if alu_commit_if,
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VX_commit_if lsu_commit_if,
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VX_commit_if mul_commit_if,
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VX_fpu_to_cmt_if fpu_commit_if,
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VX_commit_if csr_commit_if,
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VX_cmt_to_issue_if cmt_to_issue_if,
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// outputs
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VX_wb_if writeback_if
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);
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wire alu_valid = alu_commit_if.valid && cmt_to_issue_if.alu_data.wb;
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wire lsu_valid = lsu_commit_if.valid && cmt_to_issue_if.lsu_data.wb;
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wire csr_valid = csr_commit_if.valid && cmt_to_issue_if.csr_data.wb;
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wire mul_valid = mul_commit_if.valid && cmt_to_issue_if.mul_data.wb;
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wire fpu_valid = fpu_commit_if.valid && cmt_to_issue_if.fpu_data.wb;
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VX_wb_if writeback_tmp_if();
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assign writeback_tmp_if.valid = alu_valid ? alu_commit_if.valid :
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lsu_valid ? lsu_commit_if.valid :
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csr_valid ? csr_commit_if.valid :
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mul_valid ? mul_commit_if.valid :
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fpu_valid ? fpu_commit_if.valid :
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0;
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assign writeback_tmp_if.warp_num = alu_valid ? cmt_to_issue_if.alu_data.warp_num :
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lsu_valid ? cmt_to_issue_if.lsu_data.warp_num :
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csr_valid ? cmt_to_issue_if.csr_data.warp_num :
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mul_valid ? cmt_to_issue_if.mul_data.warp_num :
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fpu_valid ? cmt_to_issue_if.fpu_data.warp_num :
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0;
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assign writeback_tmp_if.curr_PC = alu_valid ? cmt_to_issue_if.alu_data.curr_PC :
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lsu_valid ? cmt_to_issue_if.lsu_data.curr_PC :
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csr_valid ? cmt_to_issue_if.csr_data.curr_PC :
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mul_valid ? cmt_to_issue_if.mul_data.curr_PC :
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fpu_valid ? cmt_to_issue_if.fpu_data.curr_PC :
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0;
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assign writeback_tmp_if.thread_mask = alu_valid ? cmt_to_issue_if.alu_data.thread_mask :
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lsu_valid ? cmt_to_issue_if.lsu_data.thread_mask :
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csr_valid ? cmt_to_issue_if.csr_data.thread_mask :
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mul_valid ? cmt_to_issue_if.mul_data.thread_mask :
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fpu_valid ? cmt_to_issue_if.fpu_data.thread_mask :
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0;
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assign writeback_tmp_if.rd = alu_valid ? cmt_to_issue_if.alu_data.rd :
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lsu_valid ? cmt_to_issue_if.lsu_data.rd :
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csr_valid ? cmt_to_issue_if.csr_data.rd :
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mul_valid ? cmt_to_issue_if.mul_data.rd :
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fpu_valid ? cmt_to_issue_if.fpu_data.rd :
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0;
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assign writeback_tmp_if.rd_is_fp = alu_valid ? 0 :
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lsu_valid ? cmt_to_issue_if.lsu_data.rd_is_fp :
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csr_valid ? 0 :
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mul_valid ? 0 :
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fpu_valid ? cmt_to_issue_if.fpu_data.rd_is_fp :
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0;
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assign writeback_tmp_if.data = alu_valid ? alu_commit_if.data :
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lsu_valid ? lsu_commit_if.data :
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csr_valid ? csr_commit_if.data :
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mul_valid ? mul_commit_if.data :
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fpu_valid ? fpu_commit_if.data :
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0;
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wire stall = ~writeback_if.ready && writeback_if.valid;
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VX_generic_register #(
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.N(1 + `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32) + 1)
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) wb_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (0),
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.in ({writeback_tmp_if.valid, writeback_tmp_if.warp_num, writeback_tmp_if.curr_PC, writeback_tmp_if.thread_mask, writeback_tmp_if.rd, writeback_tmp_if.rd_is_fp, writeback_tmp_if.data}),
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.out ({writeback_if.valid, writeback_if.warp_num, writeback_if.curr_PC, writeback_if.thread_mask, writeback_if.rd, writeback_if.rd_is_fp, writeback_if.data})
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);
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assign alu_commit_if.ready = !stall;
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assign lsu_commit_if.ready = !stall && !alu_valid;
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assign csr_commit_if.ready = !stall && !alu_valid && !lsu_valid;
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assign mul_commit_if.ready = !stall && !alu_valid && !lsu_valid && !csr_valid;
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assign fpu_commit_if.ready = !stall && !alu_valid && !lsu_valid && !csr_valid && !mul_valid;
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// special workaround to get RISC-V tests Pass status on Verilator
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reg [31:0] last_data_wb [`NUM_REGS-1:0] /* verilator public */;
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always @(posedge clk) begin
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if (writeback_tmp_if.valid && ~stall) begin
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last_data_wb[writeback_tmp_if.rd] <= writeback_tmp_if.data[0];
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end
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end
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endmodule |