233 lines
9.6 KiB
Systemverilog
233 lines
9.6 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_scoreboard import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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output reg [`PERF_CTR_BITS-1:0] perf_scb_stalls,
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output reg [`PERF_CTR_BITS-1:0] perf_units_uses [`NUM_EX_UNITS],
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output reg [`PERF_CTR_BITS-1:0] perf_sfu_uses [`NUM_SFU_UNITS],
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`endif
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VX_writeback_if.slave writeback_if [`ISSUE_WIDTH],
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VX_ibuffer_if.slave ibuffer_if [`ISSUE_WIDTH],
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VX_ibuffer_if.master scoreboard_if [`ISSUE_WIDTH]
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);
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`UNUSED_PARAM (CORE_ID)
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localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + (`NR_BITS * 4) + 1;
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`ifdef PERF_ENABLE
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reg [`ISSUE_WIDTH-1:0][`NUM_EX_UNITS-1:0] perf_issue_units_per_cycle;
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wire [`NUM_EX_UNITS-1:0] perf_units_per_cycle, perf_units_per_cycle_r;
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reg [`ISSUE_WIDTH-1:0][`NUM_SFU_UNITS-1:0] perf_issue_sfu_per_cycle;
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wire [`NUM_SFU_UNITS-1:0] perf_sfu_per_cycle, perf_sfu_per_cycle_r;
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wire [`ISSUE_WIDTH-1:0] perf_issue_stalls_per_cycle;
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wire [`CLOG2(`ISSUE_WIDTH+1)-1:0] perf_stalls_per_cycle, perf_stalls_per_cycle_r;
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`POP_COUNT(perf_stalls_per_cycle, perf_issue_stalls_per_cycle);
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VX_reduce #(
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.DATAW_IN (`NUM_EX_UNITS),
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.N (`ISSUE_WIDTH),
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.OP ("|")
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) perf_units_reduce (
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.data_in (perf_issue_units_per_cycle),
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.data_out (perf_units_per_cycle)
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);
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VX_reduce #(
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.DATAW_IN (`NUM_SFU_UNITS),
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.N (`ISSUE_WIDTH),
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.OP ("|")
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) perf_sfu_reduce (
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.data_in (perf_issue_sfu_per_cycle),
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.data_out (perf_sfu_per_cycle)
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);
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`BUFFER(perf_stalls_per_cycle_r, perf_stalls_per_cycle);
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`BUFFER(perf_units_per_cycle_r, perf_units_per_cycle);
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`BUFFER(perf_sfu_per_cycle_r, perf_sfu_per_cycle);
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always @(posedge clk) begin
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if (reset) begin
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perf_scb_stalls <= '0;
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end else begin
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perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'(perf_stalls_per_cycle_r);
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end
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end
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for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
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always @(posedge clk) begin
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if (reset) begin
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perf_units_uses[i] <= '0;
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end else begin
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perf_units_uses[i] <= perf_units_uses[i] + `PERF_CTR_BITS'(perf_units_per_cycle_r[i]);
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end
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end
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end
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for (genvar i = 0; i < `NUM_SFU_UNITS; ++i) begin
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always @(posedge clk) begin
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if (reset) begin
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perf_sfu_uses[i] <= '0;
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end else begin
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perf_sfu_uses[i] <= perf_sfu_uses[i] + `PERF_CTR_BITS'(perf_sfu_per_cycle_r[i]);
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end
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end
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end
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`endif
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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reg [`UP(ISSUE_RATIO)-1:0][`NUM_REGS-1:0] inuse_regs;
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wire writeback_fire = writeback_if[i].valid && writeback_if[i].data.eop;
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wire inuse_rd = inuse_regs[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd];
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wire inuse_rs1 = inuse_regs[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs1];
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wire inuse_rs2 = inuse_regs[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs2];
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wire inuse_rs3 = inuse_regs[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs3];
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`ifdef PERF_ENABLE
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reg [`UP(ISSUE_RATIO)-1:0][`NUM_REGS-1:0][`EX_WIDTH-1:0] inuse_units;
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reg [`UP(ISSUE_RATIO)-1:0][`NUM_REGS-1:0][`SFU_WIDTH-1:0] inuse_sfu;
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reg [`SFU_WIDTH-1:0] sfu_type;
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always @(*) begin
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case (scoreboard_if[i].data.op_type)
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`INST_SFU_CSRRW,
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`INST_SFU_CSRRS,
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`INST_SFU_CSRRC: sfu_type = `SFU_CSRS;
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default: sfu_type = `SFU_WCTL;
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endcase
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end
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always @(*) begin
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perf_issue_units_per_cycle[i] = '0;
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perf_issue_sfu_per_cycle[i] = '0;
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if (ibuffer_if[i].valid) begin
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if (inuse_rd) begin
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perf_issue_units_per_cycle[i][inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd]] = 1;
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if (inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd] == `EX_SFU) begin
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perf_issue_sfu_per_cycle[i][inuse_sfu[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd]] = 1;
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end
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end
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if (inuse_rs1) begin
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perf_issue_units_per_cycle[i][inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs1]] = 1;
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if (inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs1] == `EX_SFU) begin
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perf_issue_sfu_per_cycle[i][inuse_sfu[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs1]] = 1;
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end
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end
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if (inuse_rs2) begin
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perf_issue_units_per_cycle[i][inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs2]] = 1;
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if (inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs2] == `EX_SFU) begin
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perf_issue_sfu_per_cycle[i][inuse_sfu[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs2]] = 1;
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end
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end
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if (inuse_rs3) begin
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perf_issue_units_per_cycle[i][inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs3]] = 1;
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if (inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs3] == `EX_SFU) begin
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perf_issue_sfu_per_cycle[i][inuse_sfu[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs3]] = 1;
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end
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end
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end
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end
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assign perf_issue_stalls_per_cycle[i] = ibuffer_if[i].valid && ~ibuffer_if[i].ready;
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`endif
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reg [DATAW-1:0] data_out_r;
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reg valid_out_r;
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wire ready_out;
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wire [3:0] ready_masks = ~{inuse_rd, inuse_rs1, inuse_rs2, inuse_rs3};
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wire deps_ready = (& ready_masks);
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wire valid_in = ibuffer_if[i].valid && deps_ready;
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wire ready_in = ~valid_out_r && deps_ready;
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wire [DATAW-1:0] data_in = ibuffer_if[i].data;
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assign ready_out = scoreboard_if[i].ready;
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always @(posedge clk) begin
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if (reset) begin
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valid_out_r <= 0;
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inuse_regs <= '0;
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end else begin
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if (writeback_fire) begin
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inuse_regs[writeback_if[i].data.wis][writeback_if[i].data.rd] <= 0;
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end
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if (~valid_out_r) begin
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valid_out_r <= valid_in;
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end else if (ready_out) begin
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if (scoreboard_if[i].data.wb) begin
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inuse_regs[scoreboard_if[i].data.wis][scoreboard_if[i].data.rd] <= 1;
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`ifdef PERF_ENABLE
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inuse_units[scoreboard_if[i].data.wis][scoreboard_if[i].data.rd] <= scoreboard_if[i].data.ex_type;
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if (scoreboard_if[i].data.ex_type == `EX_SFU) begin
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inuse_sfu[scoreboard_if[i].data.wis][scoreboard_if[i].data.rd] <= sfu_type;
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end
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`endif
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end
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valid_out_r <= 0;
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end
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end
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if (~valid_out_r) begin
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data_out_r <= data_in;
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end
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end
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assign ibuffer_if[i].ready = ready_in;
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assign scoreboard_if[i].valid = valid_out_r;
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assign scoreboard_if[i].data = data_out_r;
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`ifdef SIMULATION
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reg [31:0] timeout_ctr;
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always @(posedge clk) begin
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if (reset) begin
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timeout_ctr <= '0;
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end else begin
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if (ibuffer_if[i].valid && ~ibuffer_if[i].ready) begin
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`ifdef DBG_TRACE_CORE_PIPELINE
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`TRACE(3, ("%d: *** core%0d-scoreboard-stall: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)\n",
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$time, CORE_ID, wis_to_wid(ibuffer_if[i].data.wis, i), ibuffer_if[i].data.PC, ibuffer_if[i].data.tmask, timeout_ctr,
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~ready_masks, ibuffer_if[i].data.uuid));
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`endif
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timeout_ctr <= timeout_ctr + 1;
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end else if (ibuffer_if[i].valid && ibuffer_if[i].ready) begin
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timeout_ctr <= '0;
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end
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end
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end
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`RUNTIME_ASSERT((timeout_ctr < `STALL_TIMEOUT),
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("%t: *** core%0d-scoreboard-timeout: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)",
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$time, CORE_ID, wis_to_wid(ibuffer_if[i].data.wis, i), ibuffer_if[i].data.PC, ibuffer_if[i].data.tmask, timeout_ctr,
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~ready_masks, ibuffer_if[i].data.uuid));
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`RUNTIME_ASSERT(~writeback_fire || inuse_regs[writeback_if[i].data.wis][writeback_if[i].data.rd] != 0,
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("%t: *** core%0d: invalid writeback register: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d (#%0d)",
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$time, CORE_ID, wis_to_wid(writeback_if[i].data.wis, i), writeback_if[i].data.PC, writeback_if[i].data.tmask, writeback_if[i].data.rd, writeback_if[i].data.uuid));
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`endif
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end
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endmodule
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