152 lines
4.0 KiB
C++
152 lines
4.0 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "processor.h"
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#include "processor_impl.h"
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using namespace vortex;
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ProcessorImpl::ProcessorImpl(const Arch& arch)
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: arch_(arch)
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, clusters_(arch.num_clusters())
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{
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SimPlatform::instance().initialize();
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// create memory simulator
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memsim_ = MemSim::Create("dram", MemSim::Config{
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MEMORY_BANKS,
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uint32_t(arch.num_cores()) * arch.num_clusters()
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});
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// create L3 cache
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l3cache_ = CacheSim::Create("l3cache", CacheSim::Config{
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!L3_ENABLED,
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log2ceil(L3_CACHE_SIZE), // C
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log2ceil(MEM_BLOCK_SIZE), // L
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log2ceil(L3_NUM_WAYS), // W
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0, // A
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log2ceil(L3_NUM_BANKS), // B
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XLEN, // address bits
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1, // number of ports
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uint8_t(arch.num_clusters()), // request size
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true, // write-through
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false, // write response
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L3_MSHR_SIZE, // mshr
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2, // pipeline latency
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}
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);
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// connect L3 memory ports
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l3cache_->MemReqPort.bind(&memsim_->MemReqPort);
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memsim_->MemRspPort.bind(&l3cache_->MemRspPort);
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// create clusters
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for (uint32_t i = 0; i < arch.num_clusters(); ++i) {
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clusters_.at(i) = Cluster::Create(i, this, arch, dcrs_);
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// connect L3 core ports
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clusters_.at(i)->mem_req_port.bind(&l3cache_->CoreReqPorts.at(i));
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l3cache_->CoreRspPorts.at(i).bind(&clusters_.at(i)->mem_rsp_port);
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}
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// set up memory perf recording
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memsim_->MemReqPort.tx_callback([&](const MemReq& req, uint64_t cycle){
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__unused (cycle);
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perf_mem_reads_ += !req.write;
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perf_mem_writes_ += req.write;
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perf_mem_pending_reads_ += !req.write;
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});
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memsim_->MemRspPort.tx_callback([&](const MemRsp&, uint64_t cycle){
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__unused (cycle);
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--perf_mem_pending_reads_;
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});
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this->reset();
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}
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ProcessorImpl::~ProcessorImpl() {
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SimPlatform::instance().finalize();
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}
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void ProcessorImpl::attach_ram(RAM* ram) {
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for (auto cluster : clusters_) {
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cluster->attach_ram(ram);
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}
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}
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int ProcessorImpl::run(bool riscv_test) {
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SimPlatform::instance().reset();
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this->reset();
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bool done;
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Word exitcode = 0;
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do {
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SimPlatform::instance().tick();
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done = true;
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for (auto cluster : clusters_) {
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if (cluster->running()) {
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Word ec;
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if (cluster->check_exit(&ec, riscv_test)) {
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exitcode |= ec;
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} else {
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done = false;
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}
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}
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}
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perf_mem_latency_ += perf_mem_pending_reads_;
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} while (!done);
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return exitcode;
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}
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void ProcessorImpl::reset() {
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perf_mem_reads_ = 0;
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perf_mem_writes_ = 0;
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perf_mem_latency_ = 0;
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perf_mem_pending_reads_ = 0;
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}
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void ProcessorImpl::write_dcr(uint32_t addr, uint32_t value) {
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dcrs_.write(addr, value);
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}
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ProcessorImpl::PerfStats ProcessorImpl::perf_stats() const {
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ProcessorImpl::PerfStats perf;
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perf.mem_reads = perf_mem_reads_;
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perf.mem_writes = perf_mem_writes_;
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perf.mem_latency = perf_mem_latency_;
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perf.l3cache = l3cache_->perf_stats();
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return perf;
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}
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///////////////////////////////////////////////////////////////////////////////
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Processor::Processor(const Arch& arch)
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: impl_(new ProcessorImpl(arch))
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{}
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Processor::~Processor() {
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delete impl_;
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}
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void Processor::attach_ram(RAM* mem) {
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impl_->attach_ram(mem);
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}
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int Processor::run(bool riscv_test) {
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return impl_->run(riscv_test);
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}
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void Processor::write_dcr(uint32_t addr, uint32_t value) {
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return impl_->write_dcr(addr, value);
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} |