102 lines
3.1 KiB
Verilog
102 lines
3.1 KiB
Verilog
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`include "VX_define.v"
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module VX_context (
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input wire clk,
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/* verilator lint_off UNUSED */
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input wire in_warp,
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/* verilator lint_on UNUSED */
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input wire in_wb_warp,
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input wire[`NT_M1:0] in_valid,
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input wire in_write_register,
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input wire[4:0] in_rd,
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input wire[`NT_M1:0][31:0] in_write_data,
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input wire[4:0] in_src1,
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input wire[4:0] in_src2,
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input wire in_is_clone,
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input wire in_src1_fwd,
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input wire[`NT_M1:0][31:0] in_src1_fwd_data,
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input wire in_src2_fwd,
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input wire[`NT_M1:0][31:0] in_src2_fwd_data,
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output reg[`NT_M1:0][31:0] out_a_reg_data,
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output reg[`NT_M1:0][31:0] out_b_reg_data,
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output wire out_clone_stall,
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output wire[31:0][31:0] w0_t0_registers
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);
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reg[5:0] state_stall;
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initial begin
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state_stall = 0;
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end
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wire[`NT_M1:0][31:0] rd1_register;
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wire[`NT_M1:0][31:0] rd2_register;
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/* verilator lint_off UNUSED */
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wire[31:0][31:0] clone_regsiters;
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/* verilator lint_on UNUSED */
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assign w0_t0_registers = clone_regsiters;
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VX_register_file vx_register_file_master(
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.clk (clk),
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.in_wb_warp (in_wb_warp),
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.in_valid (in_valid[0]),
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.in_write_register (in_write_register),
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.in_rd (in_rd),
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.in_data (in_write_data[0]),
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.in_src1 (in_src1),
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.in_src2 (in_src2),
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.out_regs (clone_regsiters),
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.out_src1_data (rd1_register[0]),
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.out_src2_data (rd2_register[0])
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);
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genvar index;
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generate
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for (index=1; index < `NT; index=index+1)
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begin: gen_code_label
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wire to_clone;
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assign to_clone = (index == rd1_register[0]) && (state_stall == 1);
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VX_register_file_slave vx_register_file_slave(
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.clk (clk),
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.in_warp (in_warp),
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.in_wb_warp (in_wb_warp),
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.in_valid (in_valid[index]),
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.in_write_register (in_write_register),
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.in_rd (in_rd),
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.in_data (in_write_data[index]),
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.in_src1 (in_src1),
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.in_src2 (in_src2),
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.in_clone (in_is_clone),
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.in_to_clone (to_clone),
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.in_regs (clone_regsiters),
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.out_src1_data (rd1_register[index]),
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.out_src2_data (rd2_register[index])
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);
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end
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endgenerate
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always @(posedge clk) begin
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if ((in_is_clone) && state_stall == 0) begin
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state_stall <= 10;
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end else if (state_stall == 1) begin
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state_stall <= 0;
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end else if (state_stall > 0) begin
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state_stall <= state_stall - 1;
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end
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end
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genvar index_out_reg;
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generate
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for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
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begin
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assign out_a_reg_data[index_out_reg] = ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg]);
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assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg];
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end
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endgenerate
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assign out_clone_stall = ((state_stall == 0) && in_is_clone) || ((state_stall != 1) && in_is_clone);
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endmodule |