121 lines
4.0 KiB
Verilog
121 lines
4.0 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache_dfq_queue #(
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// Size of cache in bytes
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parameter CACHE_SIZE_BYTES = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE_BYTES = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE_BYTES = 4,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Dram knobs
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parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
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) (
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input wire clk,
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input wire reset,
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input wire dfqq_push,
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input wire[NUM_BANKS-1:0] per_bank_dram_fill_req_valid,
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input wire[NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
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input wire dfqq_pop,
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output wire dfqq_req,
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output wire[31:0] dfqq_req_addr,
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output wire dfqq_empty,
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output wire dfqq_full
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);
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wire[NUM_BANKS-1:0] out_per_bank_dram_fill_req;
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wire[NUM_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr;
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reg [NUM_BANKS-1:0] use_per_bank_dram_fill_req;
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reg [NUM_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr;
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wire[NUM_BANKS-1:0] qual_bank_dram_fill_req;
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wire[NUM_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr;
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wire[NUM_BANKS-1:0] updated_bank_dram_fill_req;
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wire o_empty;
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wire use_empty = !(|use_per_bank_dram_fill_req);
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wire out_empty = !(|out_per_bank_dram_fill_req) || o_empty;
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wire push_qual = dfqq_push && !dfqq_full;
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wire pop_qual = dfqq_pop && use_empty && !out_empty;
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VX_generic_queue_ll #(
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.DATAW(NUM_BANKS * (1+32)),
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.SIZE(DFQQ_SIZE)
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) dfqq_queue (
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.clk (clk),
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.reset (reset),
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.push (push_qual),
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.in_data ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}),
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.pop (pop_qual),
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.out_data({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}),
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.empty (o_empty),
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.full (dfqq_full)
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);
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assign qual_bank_dram_fill_req = use_empty ? (out_per_bank_dram_fill_req & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req & {NUM_BANKS{!use_empty}});
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assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr;
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wire[`LOG2UP(NUM_BANKS)-1:0] qual_request_index;
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wire qual_has_request;
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VX_generic_priority_encoder #(
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.N(NUM_BANKS)
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) sel_bank (
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.valids(qual_bank_dram_fill_req),
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.index (qual_request_index),
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.found (qual_has_request)
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);
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assign dfqq_empty = !qual_has_request;
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assign dfqq_req = qual_bank_dram_fill_req [qual_request_index];
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assign dfqq_req_addr = qual_bank_dram_fill_req_addr[qual_request_index];
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assign updated_bank_dram_fill_req = qual_bank_dram_fill_req & (~(1 << qual_request_index));
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always @(posedge clk) begin
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if (reset) begin
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use_per_bank_dram_fill_req <= 0;
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use_per_bank_dram_fill_req_addr <= 0;
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end else begin
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if (dfqq_pop && qual_has_request) begin
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use_per_bank_dram_fill_req <= updated_bank_dram_fill_req;
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use_per_bank_dram_fill_req_addr <= qual_bank_dram_fill_req_addr;
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end
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end
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end
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endmodule |