108 lines
3.2 KiB
Verilog
108 lines
3.2 KiB
Verilog
`include "VX_define.vh"
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module VX_divide #(
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parameter WIDTHN = 1,
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parameter WIDTHD = 1,
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parameter NSIGNED = 0,
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parameter DSIGNED = 0,
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parameter PIPELINE = 0
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) (
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input wire clk,
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input wire reset,
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input [WIDTHN-1:0] numer,
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input [WIDTHD-1:0] denom,
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output reg [WIDTHN-1:0] quotient,
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output reg [WIDTHD-1:0] remainder
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);
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`ifdef QUARTUS
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lpm_divide quartus_div (
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.clock (clk),
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.numer (numer),
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.denom (denom),
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.quotient (quotient),
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.remain (remainder),
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.aclr (1'b0),
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.clken (1'b1)
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);
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defparam
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quartus_div.lpm_type = "LPM_DIVIDE",
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quartus_div.lpm_widthn = WIDTHN,
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quartus_div.lpm_widthd = WIDTHD,
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quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
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quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
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quartus_div.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE,MAXIMIZE_SPEED=9",
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quartus_div.lpm_pipeline = PIPELINE;
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`else
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reg [WIDTHN-1:0] quotient_unqual;
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reg [WIDTHD-1:0] remainder_unqual;
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always @(*) begin
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`ifndef SYNTHESIS
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// this edge case kills verilator in some cases by causing a division
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// overflow exception. INT_MIN / -1 (on x86)
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if (numer == {1'b1, (WIDTHN-1)'(0)}
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&& denom == {WIDTHD{1'b1}}) begin
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quotient_unqual = 0;
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remainder_unqual = 0;
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end else
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`endif
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begin
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if (NSIGNED && DSIGNED) begin
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quotient_unqual = $signed(numer) / $signed(denom);
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remainder_unqual = $signed(numer) % $signed(denom);
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end
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else if (NSIGNED && !DSIGNED) begin
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quotient_unqual = $signed(numer) / denom;
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remainder_unqual = $signed(numer) % denom;
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end
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else if (!NSIGNED && DSIGNED) begin
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quotient_unqual = numer / $signed(denom);
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remainder_unqual = numer % $signed(denom);
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end
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else begin
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quotient_unqual = numer / denom;
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remainder_unqual = numer % denom;
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end
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end
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end
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if (PIPELINE == 0) begin
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assign quotient = quotient_unqual;
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assign remainder = remainder_unqual;
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end else begin
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reg [WIDTHN-1:0] quotient_pipe [0:PIPELINE-1];
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reg [WIDTHD-1:0] remainder_pipe [0:PIPELINE-1];
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genvar i;
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for (i = 0; i < PIPELINE; i++) begin
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always @(posedge clk) begin
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if (reset) begin
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quotient_pipe[i] <= 0;
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remainder_pipe[i] <= 0;
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end
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else begin
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if (i == 0) begin
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quotient_pipe[0] <= quotient_unqual;
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remainder_pipe[0] <= remainder_unqual;
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end else begin
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quotient_pipe[i] <= quotient_pipe[i-1];
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remainder_pipe[i] <= remainder_pipe[i-1];
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end
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end
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end
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end
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assign quotient = quotient_pipe[PIPELINE-1];
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assign remainder = remainder_pipe[PIPELINE-1];
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end
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`endif
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endmodule |