16 lines
215 B
Verilog
16 lines
215 B
Verilog
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`include "../VX_define.v"
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`ifndef VX_DCACHE_RSP
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`define VX_DCACHE_RSP
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interface VX_dcache_response_inter ();
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wire[`NT_M1:0][31:0] in_cache_driver_out_data;
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wire delay;
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endinterface
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`endif |