525 lines
9.1 KiB
Systemverilog
525 lines
9.1 KiB
Systemverilog
`ifndef VX_CONFIG
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`define VX_CONFIG
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`include "VX_user_config.vh"
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`ifndef NUM_CLUSTERS
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`define NUM_CLUSTERS 1
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`endif
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`ifndef NUM_CORES
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`define NUM_CORES 1
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`endif
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`ifndef NUM_WARPS
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`define NUM_WARPS 8
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`endif
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`ifndef NUM_THREADS
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`define NUM_THREADS 4
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`endif
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`ifndef NUM_BARRIERS
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`define NUM_BARRIERS 4
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`endif
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`ifndef GLOBAL_BLOCK_SIZE
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`define GLOBAL_BLOCK_SIZE 16
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`endif
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`ifndef NUM_CSRS
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`define NUM_CSRS 2
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`endif
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`ifndef STARTUP_ADDR
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`define STARTUP_ADDR 32'h80000000
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`endif
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`ifndef SHARED_MEM_TOP_ADDR
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`define SHARED_MEM_TOP_ADDR 8'hFE
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`endif
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`ifndef STACK_BASE_ADDR
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`define STACK_BASE_ADDR 20'h6FFFF
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`endif
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`ifndef IO_BUS_BASE_ADDR
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`define IO_BUS_BASE_ADDR 32'hFFFFFF00
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`endif
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`ifndef IO_BUS_ADDR_COUT
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`define IO_BUS_ADDR_COUT 32'hFFFFFFFC
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`endif
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`ifndef L2_ENABLE
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`define L2_ENABLE (`NUM_CORES > 1)
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`endif
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`define CSR_LTID 12'h020
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`define CSR_LWID 12'h021
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`define CSR_GWID 12'h022
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`define CSR_GTID 12'h023
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`define CSR_CYCLL 12'hC00
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`define CSR_CYCLH 12'hC80
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`define CSR_INSTL 12'hC02
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`define CSR_INSTH 12'hC82
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// ========================= Dcache Configurable Knobs ========================
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// Size of cache in bytes
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`ifndef DCACHE_SIZE
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`define DCACHE_SIZE 2048
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`endif
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// Size of line inside a bank in bytes
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`ifndef DBANK_LINE_SIZE
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`define DBANK_LINE_SIZE `GLOBAL_BLOCK_SIZE
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`endif
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// Number of banks {1, 2, 4, 8,...}
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`ifndef DNUM_BANKS
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`define DNUM_BANKS 8
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`endif
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// Size of a word in bytes
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`ifndef DWORD_SIZE
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`define DWORD_SIZE 4
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`endif
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`ifndef DNUM_REQUESTS
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`define DNUM_REQUESTS `NUM_THREADS
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`endif
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// Number of cycles to complete stage 1 (read from memory)
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`ifndef DSTAGE_1_CYCLES
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`define DSTAGE_1_CYCLES 1
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`endif
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// Core Request Queue Size
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`ifndef DREQQ_SIZE
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`define DREQQ_SIZE `NUM_WARPS
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`endif
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// Miss Reserv Queue Knob
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`ifndef DMRVQ_SIZE
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`define DMRVQ_SIZE (`NUM_WARPS*`NUM_THREADS)
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`endif
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// Dram Fill Rsp Queue Size
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`ifndef DDFPQ_SIZE
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`define DDFPQ_SIZE 32
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`endif
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// Snoop Req Queue
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`ifndef DSNRQ_SIZE
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`define DSNRQ_SIZE 32
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`endif
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// Core Writeback Queue Size
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`ifndef DCWBQ_SIZE
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`define DCWBQ_SIZE `DREQQ_SIZE
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`endif
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// Dram Writeback Queue Size
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`ifndef DDWBQ_SIZE
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`define DDWBQ_SIZE 4
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`endif
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// Dram Fill Req Queue Size
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`ifndef DDFQQ_SIZE
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`define DDFQQ_SIZE `DREQQ_SIZE
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`endif
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// Lower Level Cache Hit Queue Size
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`ifndef DLLVQ_SIZE
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`define DLLVQ_SIZE 0
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`endif
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// Fill Forward SNP Queue
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`ifndef DFFSQ_SIZE
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`define DFFSQ_SIZE 32
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`endif
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// Prefetcher
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`ifndef DPRFQ_SIZE
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`define DPRFQ_SIZE 32
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`endif
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`ifndef DPRFQ_STRIDE
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`define DPRFQ_STRIDE 0
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`endif
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// Fill Invalidator Size {Fill invalidator must be active}
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`ifndef DFILL_INVALIDAOR_SIZE
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`define DFILL_INVALIDAOR_SIZE 32
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`endif
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// ========================== Icache Configurable Knobs =======================
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// Size of cache in bytes
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`ifndef ICACHE_SIZE
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`define ICACHE_SIZE 2048
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`endif
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// Size of line inside a bank in bytes
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`ifndef IBANK_LINE_SIZE
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`define IBANK_LINE_SIZE `GLOBAL_BLOCK_SIZE
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`endif
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// Number of banks {1, 2, 4, 8,...}
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`ifndef INUM_BANKS
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`define INUM_BANKS 8
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`endif
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// Size of a word in bytes
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`ifndef IWORD_SIZE
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`define IWORD_SIZE 4
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`endif
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`ifndef INUM_REQUESTS
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`define INUM_REQUESTS 1
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`endif
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// Number of cycles to complete stage 1 (read from memory)
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`ifndef ISTAGE_1_CYCLES
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`define ISTAGE_1_CYCLES 1
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`endif
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// Core Request Queue Size
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`ifndef IREQQ_SIZE
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`define IREQQ_SIZE `NUM_WARPS
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`endif
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// Miss Reserv Queue Knob
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`ifndef IMRVQ_SIZE
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`define IMRVQ_SIZE `IREQQ_SIZE
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`endif
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// Dram Fill Rsp Queue Size
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`ifndef IDFPQ_SIZE
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`define IDFPQ_SIZE 32
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`endif
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// Snoop Req Queue
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`ifndef ISNRQ_SIZE
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`define ISNRQ_SIZE 32
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`endif
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// Core Writeback Queue Size
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`ifndef ICWBQ_SIZE
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`define ICWBQ_SIZE `IREQQ_SIZE
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`endif
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// Dram Writeback Queue Size
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`ifndef IDWBQ_SIZE
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`define IDWBQ_SIZE 16
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`endif
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// Dram Fill Req Queue Size
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`ifndef IDFQQ_SIZE
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`define IDFQQ_SIZE `IREQQ_SIZE
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`endif
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// Lower Level Cache Hit Queue Size
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`ifndef ILLVQ_SIZE
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`define ILLVQ_SIZE 16
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`endif
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// Fill Forward SNP Queue
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`ifndef IFFSQ_SIZE
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`define IFFSQ_SIZE 8
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`endif
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// Prefetcher
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`ifndef IPRFQ_SIZE
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`define IPRFQ_SIZE 32
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`endif
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`ifndef IPRFQ_STRIDE
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`define IPRFQ_STRIDE 0
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`endif
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// Fill Invalidator Size {Fill invalidator must be active}
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`ifndef IFILL_INVALIDAOR_SIZE
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`define IFILL_INVALIDAOR_SIZE 32
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`endif
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// =========================== SM Configurable Knobs ==========================
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// Size of cache in bytes
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`ifndef SCACHE_SIZE
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`define SCACHE_SIZE 1024
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`endif
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// Size of line inside a bank in bytes
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`ifndef SBANK_LINE_SIZE
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`define SBANK_LINE_SIZE `GLOBAL_BLOCK_SIZE
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`endif
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// Number of banks {1, 2, 4, 8,...}
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`ifndef SNUM_BANKS
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`define SNUM_BANKS 8
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`endif
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// Size of a word in bytes
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`ifndef SWORD_SIZE
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`define SWORD_SIZE 4
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`endif
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`ifndef SNUM_REQUESTS
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`define SNUM_REQUESTS `NUM_THREADS
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`endif
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// Number of cycles to complete stage 1 (read from memory)
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`ifndef SSTAGE_1_CYCLES
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`define SSTAGE_1_CYCLES 1
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`endif
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// Core Request Queue Size
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`ifndef SREQQ_SIZE
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`define SREQQ_SIZE `NUM_WARPS
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`endif
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// Miss Reserv Queue Knob
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`ifndef SMRVQ_SIZE
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`define SMRVQ_SIZE `SREQQ_SIZE
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`endif
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// Dram Fill Rsp Queue Size
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`ifndef SDFPQ_SIZE
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`define SDFPQ_SIZE 0
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`endif
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// Snoop Req Queue
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`ifndef SSNRQ_SIZE
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`define SSNRQ_SIZE 16
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`endif
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// Core Writeback Queue Size
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`ifndef SCWBQ_SIZE
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`define SCWBQ_SIZE `SREQQ_SIZE
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`endif
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// Dram Writeback Queue Size
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`ifndef SDWBQ_SIZE
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`define SDWBQ_SIZE 16
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`endif
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// Dram Fill Req Queue Size
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`ifndef SDFQQ_SIZE
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`define SDFQQ_SIZE 16
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`endif
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// Lower Level Cache Hit Queue Size
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`ifndef SLLVQ_SIZE
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`define SLLVQ_SIZE 16
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`endif
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// Fill Forward SNP Queue
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`ifndef SFFSQ_SIZE
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`define SFFSQ_SIZE 16
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`endif
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// Prefetcher
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`ifndef SPRFQ_SIZE
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`define SPRFQ_SIZE 4
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`endif
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`ifndef SPRFQ_STRIDE
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`define SPRFQ_STRIDE 0
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`endif
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// Fill Invalidator Size {Fill invalidator must be active}
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`ifndef SFILL_INVALIDAOR_SIZE
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`define SFILL_INVALIDAOR_SIZE 32
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`endif
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// ======================== L2cache Configurable Knobs ========================
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// Size of cache in bytes
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`ifndef L2CACHE_SIZE
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`define L2CACHE_SIZE 4096
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`endif
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// Size of line inside a bank in bytes
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`ifndef L2BANK_LINE_SIZE
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`define L2BANK_LINE_SIZE `GLOBAL_BLOCK_SIZE
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`endif
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// Number of banks {1, 2, 4, 8,...}
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`ifndef L2NUM_BANKS
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`define L2NUM_BANKS 8
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`endif
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// Size of a word in bytes
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`ifndef L2WORD_SIZE
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`define L2WORD_SIZE `L2BANK_LINE_SIZE
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`endif
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`ifndef L2NUM_REQUESTS
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`define L2NUM_REQUESTS (2*`NUM_CORES)
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`endif
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// Number of cycles to complete stage 1 (read from memory)
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`ifndef L2STAGE_1_CYCLES
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`define L2STAGE_1_CYCLES 1
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`endif
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// Core Request Queue Size
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`ifndef L2REQQ_SIZE
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`define L2REQQ_SIZE 32
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`endif
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// Miss Reserv Queue Knob
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`ifndef L2MRVQ_SIZE
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`define L2MRVQ_SIZE 32
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`endif
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// Dram Fill Rsp Queue Size
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`ifndef L2DFPQ_SIZE
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`define L2DFPQ_SIZE 32
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`endif
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// Snoop Req Queue
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`ifndef L2SNRQ_SIZE
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`define L2SNRQ_SIZE 32
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`endif
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// Core Writeback Queue Size
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`ifndef L2CWBQ_SIZE
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`define L2CWBQ_SIZE `L2REQQ_SIZE
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`endif
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// Dram Writeback Queue Size
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`ifndef L2DWBQ_SIZE
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`define L2DWBQ_SIZE 16
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`endif
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// Dram Fill Req Queue Size
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`ifndef L2DFQQ_SIZE
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`define L2DFQQ_SIZE `L2REQQ_SIZE
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`endif
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// Lower Level Cache Hit Queue Size
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`ifndef L2LLVQ_SIZE
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`define L2LLVQ_SIZE 32
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`endif
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// Fill Forward SNP Queue
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`ifndef L2FFSQ_SIZE
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`define L2FFSQ_SIZE 32
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`endif
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// Prefetcher
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`ifndef L2PRFQ_SIZE
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`define L2PRFQ_SIZE 32
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`endif
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`ifndef L2PRFQ_STRIDE
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`define L2PRFQ_STRIDE 0
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`endif
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// Fill Invalidator Size {Fill invalidator must be active}
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`ifndef L2FILL_INVALIDAOR_SIZE
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`define L2FILL_INVALIDAOR_SIZE 32
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`endif
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// ======================== L3cache Configurable Knobs ========================
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// Size of cache in bytes
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`ifndef L3CACHE_SIZE
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`define L3CACHE_SIZE 8192
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`endif
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// Size of line inside a bank in bytes
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`ifndef L3BANK_LINE_SIZE
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`define L3BANK_LINE_SIZE `GLOBAL_BLOCK_SIZE
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`endif
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// Number of banks {1, 2, 4, 8,...}
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`ifndef L3NUM_BANKS
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`define L3NUM_BANKS 8
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`endif
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// Size of a word in bytes
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`ifndef L3WORD_SIZE
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`define L3WORD_SIZE `L3BANK_LINE_SIZE
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`endif
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`ifndef L3NUM_REQUESTS
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`define L3NUM_REQUESTS `NUM_CLUSTERS
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`endif
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// Number of cycles to complete stage 1 (read from memory)
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`ifndef L3STAGE_1_CYCLES
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`define L3STAGE_1_CYCLES 1
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`endif
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// Core Request Queue Size
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`ifndef L3REQQ_SIZE
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`define L3REQQ_SIZE 32
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`endif
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// Miss Reserv Queue Knob
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`ifndef L3MRVQ_SIZE
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`define L3MRVQ_SIZE `L3REQQ_SIZE
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`endif
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// Dram Fill Rsp Queue Size
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`ifndef L3DFPQ_SIZE
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`define L3DFPQ_SIZE 32
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`endif
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// Snoop Req Queue
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`ifndef L3SNRQ_SIZE
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`define L3SNRQ_SIZE 32
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`endif
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// Core Writeback Queue Size
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`ifndef L3CWBQ_SIZE
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`define L3CWBQ_SIZE `L3REQQ_SIZE
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`endif
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// Dram Writeback Queue Size
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`ifndef L3DWBQ_SIZE
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`define L3DWBQ_SIZE 16
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`endif
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// Dram Fill Req Queue Size
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`ifndef L3DFQQ_SIZE
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`define L3DFQQ_SIZE `L3REQQ_SIZE
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`endif
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// Lower Level Cache Hit Queue Size
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`ifndef L3LLVQ_SIZE
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`define L3LLVQ_SIZE 0
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`endif
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// Fill Forward SNP Queue
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`ifndef L3FFSQ_SIZE
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`define L3FFSQ_SIZE 8
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`endif
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// Prefetcher
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`ifndef L3PRFQ_SIZE
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`define L3PRFQ_SIZE 32
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`endif
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`ifndef L3PRFQ_STRIDE
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`define L3PRFQ_STRIDE 0
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`endif
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// Fill Invalidator Size {Fill invalidator must be active}
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`ifndef L3FILL_INVALIDAOR_SIZE
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`define L3FILL_INVALIDAOR_SIZE 32
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`endif
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// VX_CONFIG
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`endif
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