650 lines
27 KiB
Verilog
650 lines
27 KiB
Verilog
`include "VX_cache_config.vh"
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`include "VX_define.vh"
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module VX_bank #(
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// Size of cache in bytes
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parameter CACHE_SIZE = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Forward SNP Queue
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parameter FFSQ_SIZE = 8,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Enable dram update
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parameter DRAM_ENABLE = 1,
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// Enable snoop forwarding
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parameter SNOOP_FORWARDING_ENABLE = 0,
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// core request tag size
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parameter CORE_TAG_WIDTH = 1,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = 0
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) (
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input wire clk,
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input wire reset,
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// Core Request
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input wire core_req_ready,
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input wire [NUM_REQUESTS-1:0] core_req_valids,
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input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_read,
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input wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_write,
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input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
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input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
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input wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
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output wire core_req_full,
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// Core Response
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output wire core_rsp_valid,
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output wire [`LOG2UP(NUM_REQUESTS)-1:0] core_rsp_tid,
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output wire [`WORD_WIDTH-1:0] core_rsp_data,
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output wire [CORE_TAG_WIDTH-1:0] core_rsp_tag,
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input wire core_rsp_pop,
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// Dram Fill Requests
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output wire dram_fill_req_valid,
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output wire[`LINE_ADDR_WIDTH-1:0] dram_fill_req_addr,
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output wire dram_fill_req_is_snp,
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input wire dram_fill_req_full,
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// Dram Fill Response
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input wire dram_fill_rsp_valid,
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input wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dram_fill_rsp_data,
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input wire [`LINE_ADDR_WIDTH-1:0] dram_fill_rsp_addr,
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output wire dram_fill_rsp_ready,
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// Dram WB Requests
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output wire dram_wb_req_valid,
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output wire [`LINE_ADDR_WIDTH-1:0] dram_wb_req_addr,
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output wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dram_wb_req_data,
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input wire dram_wb_req_pop,
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// Snp Request
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input wire snp_req_valid,
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input wire [`LINE_ADDR_WIDTH-1:0] snp_req_addr,
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output wire snp_req_full,
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output wire snp_fwd_valid,
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output wire [`LINE_ADDR_WIDTH-1:0] snp_fwd_addr,
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input wire snp_fwd_pop
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);
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reg snoop_state = 0;
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always @(posedge clk) begin
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if (reset) begin
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snoop_state <= 0;
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end else begin
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snoop_state <= (snoop_state | snp_req_valid) && SNOOP_FORWARDING_ENABLE;
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end
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end
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wire snrq_pop;
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wire snrq_empty;
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wire snrq_valid_st0;
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wire[`LINE_ADDR_WIDTH-1:0] snrq_addr_st0;
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assign snrq_valid_st0 = !snrq_empty;
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VX_generic_queue #(
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.DATAW($bits(snp_req_addr)),
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.SIZE(SNRQ_SIZE)
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) snr_queue (
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.clk (clk),
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.reset (reset),
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.push (snp_req_valid),
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.data_in (snp_req_addr),
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.pop (snrq_pop),
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.data_out(snrq_addr_st0),
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.empty (snrq_empty),
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.full (snp_req_full)
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);
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wire dfpq_pop;
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wire dfpq_empty;
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wire dfpq_full;
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wire [`LINE_ADDR_WIDTH-1:0] dfpq_addr_st0;
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wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dfpq_filldata_st0;
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assign dram_fill_rsp_ready = !dfpq_full;
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VX_generic_queue #(
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.DATAW($bits(dram_fill_rsp_addr) + $bits(dram_fill_rsp_data)),
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.SIZE(DFPQ_SIZE)
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) dfp_queue (
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.clk (clk),
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.reset (reset),
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.push (dram_fill_rsp_valid),
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.data_in ({dram_fill_rsp_addr, dram_fill_rsp_data}),
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.pop (dfpq_pop),
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.data_out({dfpq_addr_st0, dfpq_filldata_st0}),
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.empty (dfpq_empty),
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.full (dfpq_full)
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);
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wire reqq_pop;
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wire reqq_push;
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wire reqq_empty;
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wire reqq_req_st0;
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wire[`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0;
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`IGNORE_WARNINGS_BEGIN
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wire [31:0] reqq_req_addr_st0;
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`IGNORE_WARNINGS_END
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wire [`WORD_WIDTH-1:0] reqq_req_writeword_st0;
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wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0;
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wire [`BYTE_EN_BITS-1:0] reqq_req_mem_read_st0;
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wire [`BYTE_EN_BITS-1:0] reqq_req_mem_write_st0;
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assign reqq_push = core_req_ready && (|core_req_valids);
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VX_cache_req_queue #(
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.CACHE_SIZE (CACHE_SIZE),
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
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) req_queue (
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.clk (clk),
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.reset (reset),
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// Enqueue
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.reqq_push (reqq_push),
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.bank_valids (core_req_valids),
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.bank_addr (core_req_addr),
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.bank_writedata (core_req_data),
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.bank_tag (core_req_tag),
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.bank_mem_read (core_req_read),
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.bank_mem_write (core_req_write),
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// Dequeue
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.reqq_pop (reqq_pop),
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.reqq_req_st0 (reqq_req_st0),
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.reqq_req_tid_st0 (reqq_req_tid_st0),
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.reqq_req_addr_st0 (reqq_req_addr_st0),
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.reqq_req_writedata_st0(reqq_req_writeword_st0),
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.reqq_req_tag_st0 (reqq_req_tag_st0),
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.reqq_req_mem_read_st0 (reqq_req_mem_read_st0),
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.reqq_req_mem_write_st0(reqq_req_mem_write_st0),
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.reqq_empty (reqq_empty),
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.reqq_full (core_req_full)
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);
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wire mrvq_pop;
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wire mrvq_full;
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wire mrvq_stop;
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wire mrvq_valid_st0;
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wire[`LOG2UP(NUM_REQUESTS)-1:0] mrvq_tid_st0;
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wire [`LINE_ADDR_WIDTH-1:0] mrvq_addr_st0;
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wire [`BASE_ADDR_BITS-1:0] mrvq_wsel_st0;
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wire [`WORD_WIDTH-1:0] mrvq_writeword_st0;
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wire [CORE_TAG_WIDTH-1:0] mrvq_tag_st0;
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wire [`BYTE_EN_BITS-1:0] mrvq_mem_read_st0;
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wire [`BYTE_EN_BITS-1:0] mrvq_mem_write_st0;
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wire miss_add;
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wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr;
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wire[`BASE_ADDR_BITS-1:0] miss_add_wsel;
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wire[`WORD_WIDTH-1:0] miss_add_data;
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wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_add_tid;
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wire[CORE_TAG_WIDTH-1:0] miss_add_tag;
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wire[`BYTE_EN_BITS-1:0] miss_add_mem_read;
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wire[`BYTE_EN_BITS-1:0] miss_add_mem_write;
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wire[`LINE_ADDR_WIDTH-1:0] addr_st2;
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wire is_fill_st2;
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wire stall_bank_pipe;
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reg is_fill_in_pipe;
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wire is_fill_st1 [STAGE_1_CYCLES-1:0];
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`DEBUG_BEGIN
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wire going_to_write_st1[STAGE_1_CYCLES-1:0];
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`DEBUG_END
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integer i;
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always @(*) begin
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is_fill_in_pipe = 0;
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for (i = 0; i < STAGE_1_CYCLES; i=i+1) begin
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if (is_fill_st1[i]) begin
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is_fill_in_pipe = 1;
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end
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end
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if (is_fill_st2) begin
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is_fill_in_pipe = 1;
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end
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end
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assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe;
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assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe;
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assign reqq_pop = !mrvq_stop && !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !is_fill_in_pipe;
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assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe;
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wire qual_is_fill_st0;
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wire qual_valid_st0;
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wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0;
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wire [`WORD_SELECT_ADDR_END:0] qual_wsel_st0;
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wire [`WORD_WIDTH-1:0] qual_writeword_st0;
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wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] qual_writedata_st0;
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wire [`REQ_INST_META_WIDTH-1:0] qual_inst_meta_st0;
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wire qual_going_to_write_st0;
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wire qual_is_snp;
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wire valid_st1 [STAGE_1_CYCLES-1:0];
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wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0];
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wire [`WORD_SELECT_ADDR_END:0] wsel_st1 [STAGE_1_CYCLES-1:0];
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wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0];
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wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
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wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] writedata_st1[STAGE_1_CYCLES-1:0];
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wire is_snp_st1 [STAGE_1_CYCLES-1:0];
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assign qual_is_fill_st0 = dfpq_pop;
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assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop;
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assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 :
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mrvq_pop ? mrvq_addr_st0 :
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reqq_pop ? reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] :
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snrq_pop ? snrq_addr_st0 :
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0;
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assign qual_wsel_st0 = reqq_pop ? reqq_req_addr_st0[`BASE_ADDR_BITS-1:0] :
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mrvq_pop ? mrvq_wsel_st0 :
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0;
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assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 57;
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assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_tag_st0 , mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} :
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reqq_pop ? {reqq_req_tag_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
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0;
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assign qual_going_to_write_st0 = dfpq_pop ? 1 :
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(mrvq_pop && (mrvq_mem_write_st0 != `BYTE_EN_NO)) ? 1 :
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(reqq_pop && (reqq_req_mem_write_st0 != `BYTE_EN_NO)) ? 1 :
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(snrq_pop) ? 1 :
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0;
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assign qual_is_snp = snrq_pop ? 1 : 0;
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assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 :
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reqq_pop ? reqq_req_writeword_st0 :
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0;
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VX_generic_register #(
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.N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + (`BANK_LINE_WORDS*`WORD_WIDTH))
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) s0_1_c0 (
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.clk (clk),
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.reset (reset),
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.stall (stall_bank_pipe),
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.flush (0),
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.in ({qual_is_snp, qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_wsel_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}),
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.out ({is_snp_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]})
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);
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genvar stage;
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for (stage = 1; stage < STAGE_1_CYCLES; stage = stage + 1) begin
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VX_generic_register #(
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.N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + (`BANK_LINE_WORDS*`WORD_WIDTH))
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) s0_1_cc (
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.clk (clk),
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.reset(reset),
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.stall(stall_bank_pipe),
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.flush(0),
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.in ({is_snp_st1[stage-1], going_to_write_st1[stage-1], valid_st1[stage-1], addr_st1[stage-1], wsel_st1[stage-1], writeword_st1[stage-1], inst_meta_st1[stage-1], is_fill_st1[stage-1], writedata_st1[stage-1]}),
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.out ({is_snp_st1[stage], going_to_write_st1[stage], valid_st1[stage], addr_st1[stage], wsel_st1[stage], writeword_st1[stage], inst_meta_st1[stage], is_fill_st1[stage], writedata_st1[stage]})
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);
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end
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wire[`WORD_WIDTH-1:0] readword_st1e;
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wire[`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] readdata_st1e;
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wire[`TAG_SELECT_BITS-1:0] readtag_st1e;
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wire miss_st1e;
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wire dirty_st1e;
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`DEBUG_BEGIN
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wire [CORE_TAG_WIDTH-1:0] tag_st1e;
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wire [`LOG2UP(NUM_REQUESTS)-1:0] tid_st1e;
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`DEBUG_END
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wire [`BYTE_EN_BITS-1:0] mem_read_st1e;
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wire [`BYTE_EN_BITS-1:0] mem_write_st1e;
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wire fill_saw_dirty_st1e;
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wire is_snp_st1e;
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assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1];
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assign {tag_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
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VX_tag_data_access #(
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.CACHE_SIZE (CACHE_SIZE),
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.DRAM_ENABLE (DRAM_ENABLE),
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.WRITE_ENABLE (WRITE_ENABLE)
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) tag_data_access (
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.clk (clk),
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.reset (reset),
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.stall (stall_bank_pipe),
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.stall_bank_pipe(stall_bank_pipe),
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// Initial Read
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.readaddr_st10 (addr_st1[0][`LINE_SELECT_BITS-1:0]),
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// Actual Read/Write
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.valid_req_st1e(valid_st1[STAGE_1_CYCLES-1]),
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.writefill_st1e(is_fill_st1[STAGE_1_CYCLES-1]),
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.writeaddr_st1e(addr_st1[STAGE_1_CYCLES-1]),
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.writewsel_st1e(wsel_st1[STAGE_1_CYCLES-1]),
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.writeword_st1e(writeword_st1[STAGE_1_CYCLES-1]),
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.writedata_st1e(writedata_st1[STAGE_1_CYCLES-1]),
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.mem_write_st1e(mem_write_st1e),
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.mem_read_st1e (mem_read_st1e),
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.is_snp_st1e (is_snp_st1e),
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// Read Data
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.readword_st1e (readword_st1e),
|
|
.readdata_st1e (readdata_st1e),
|
|
.readtag_st1e (readtag_st1e),
|
|
.miss_st1e (miss_st1e),
|
|
.dirty_st1e (dirty_st1e),
|
|
.fill_saw_dirty_st1e(fill_saw_dirty_st1e)
|
|
);
|
|
|
|
wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1];
|
|
|
|
wire valid_st2;
|
|
wire [`BASE_ADDR_BITS-1:0] wsel_st2;
|
|
wire [`WORD_WIDTH-1:0] writeword_st2;
|
|
wire [`WORD_WIDTH-1:0] readword_st2;
|
|
wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] readdata_st2;
|
|
wire miss_st2;
|
|
wire dirty_st2;
|
|
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st2;
|
|
wire [`TAG_SELECT_BITS-1:0] readtag_st2;
|
|
wire fill_saw_dirty_st2;
|
|
wire is_snp_st2;
|
|
|
|
VX_generic_register #(
|
|
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + (`BANK_LINE_WORDS * `WORD_WIDTH) + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH)
|
|
) st_1e_2 (
|
|
.clk (clk),
|
|
.reset(reset),
|
|
.stall(stall_bank_pipe),
|
|
.flush(0),
|
|
.in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
|
|
.out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
|
|
);
|
|
|
|
wire should_flush;
|
|
wire dwbq_push;
|
|
|
|
wire cwbq_full;
|
|
wire dwbq_full;
|
|
wire ffsq_full;
|
|
wire invalidate_fill;
|
|
|
|
// Enqueue to miss reserv if it's a valid miss
|
|
assign miss_add = valid_st2
|
|
&& !is_snp_st2
|
|
&& miss_st2
|
|
&& !mrvq_full
|
|
&& !(should_flush && dwbq_push)
|
|
&& !((is_snp_st2 && valid_st2 && ffsq_full)
|
|
|| ((valid_st2 && !miss_st2) && cwbq_full)
|
|
|| (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full)
|
|
|| (valid_st2 && miss_st2 && mrvq_full)
|
|
|| (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
|
|
|
|
assign miss_add_addr = addr_st2;
|
|
assign miss_add_wsel = wsel_st2;
|
|
assign miss_add_data = writeword_st2;
|
|
assign {miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
|
|
|
|
VX_cache_miss_resrv #(
|
|
.CACHE_SIZE (CACHE_SIZE),
|
|
.BANK_LINE_SIZE (BANK_LINE_SIZE),
|
|
.NUM_BANKS (NUM_BANKS),
|
|
.WORD_SIZE (WORD_SIZE),
|
|
.NUM_REQUESTS (NUM_REQUESTS),
|
|
.STAGE_1_CYCLES (STAGE_1_CYCLES),
|
|
.REQQ_SIZE (REQQ_SIZE),
|
|
.MRVQ_SIZE (MRVQ_SIZE),
|
|
.DFPQ_SIZE (DFPQ_SIZE),
|
|
.SNRQ_SIZE (SNRQ_SIZE),
|
|
.CWBQ_SIZE (CWBQ_SIZE),
|
|
.DWBQ_SIZE (DWBQ_SIZE),
|
|
.DFQQ_SIZE (DFQQ_SIZE),
|
|
.LLVQ_SIZE (LLVQ_SIZE),
|
|
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
|
|
.CORE_TAG_WIDTH (CORE_TAG_WIDTH)
|
|
) cache_miss_resrv (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
// Enqueue
|
|
.miss_add (miss_add), // Need to do all
|
|
.miss_add_addr (miss_add_addr),
|
|
.miss_add_wsel (miss_add_wsel),
|
|
.miss_add_data (miss_add_data),
|
|
.miss_add_tid (miss_add_tid),
|
|
.miss_add_tag (miss_add_tag),
|
|
.miss_add_mem_read (miss_add_mem_read),
|
|
.miss_add_mem_write (miss_add_mem_write),
|
|
.miss_resrv_full (mrvq_full),
|
|
.miss_resrv_stop (mrvq_stop),
|
|
|
|
// Broadcast
|
|
.is_fill_st1 (is_fill_st2),
|
|
.fill_addr_st1 (addr_st2),
|
|
|
|
// Dequeue
|
|
.miss_resrv_pop (mrvq_pop),
|
|
.miss_resrv_valid_st0 (mrvq_valid_st0),
|
|
.miss_resrv_addr_st0 (mrvq_addr_st0),
|
|
.miss_resrv_wsel_st0 (mrvq_wsel_st0),
|
|
.miss_resrv_data_st0 (mrvq_writeword_st0),
|
|
.miss_resrv_tid_st0 (mrvq_tid_st0),
|
|
.miss_resrv_tag_st0 (mrvq_tag_st0),
|
|
.miss_resrv_mem_read_st0 (mrvq_mem_read_st0),
|
|
.miss_resrv_mem_write_st0(mrvq_mem_write_st0)
|
|
);
|
|
|
|
// Enqueue to CWB Queue
|
|
wire cwbq_push = (valid_st2 && !miss_st2)
|
|
&& !cwbq_full
|
|
&& !(SNOOP_FORWARDING_ENABLE && (miss_add_mem_write == `BYTE_EN_NO))
|
|
&& !((is_snp_st2 && valid_st2 && ffsq_full)
|
|
|| (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full)
|
|
|| (valid_st2 && miss_st2 && mrvq_full)
|
|
|| (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
|
|
|
|
wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2;
|
|
wire [`LOG2UP(NUM_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
|
|
wire [CORE_TAG_WIDTH-1:0] cwbq_tag = miss_add_tag;
|
|
|
|
wire cwbq_empty;
|
|
assign core_rsp_valid = !cwbq_empty;
|
|
VX_generic_queue #(
|
|
.DATAW(`LOG2UP(NUM_REQUESTS) + CORE_TAG_WIDTH + `WORD_WIDTH),
|
|
.SIZE(CWBQ_SIZE)
|
|
) cwb_queue (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
|
|
.push (cwbq_push),
|
|
.data_in ({cwbq_tid, cwbq_tag, cwbq_data}),
|
|
|
|
.pop (core_rsp_pop),
|
|
.data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}),
|
|
.empty (cwbq_empty),
|
|
.full (cwbq_full)
|
|
);
|
|
|
|
assign should_flush = snoop_state
|
|
&& valid_st2
|
|
&& (miss_add_mem_write != `BYTE_EN_NO)
|
|
&& !is_snp_st2 && !is_fill_st2;
|
|
|
|
// Enqueue to DWB Queue
|
|
assign dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2 || should_flush)
|
|
&& !dwbq_full
|
|
&& !((is_snp_st2 && valid_st2 && ffsq_full)
|
|
|| ((valid_st2 && !miss_st2) && cwbq_full)
|
|
|| (valid_st2 && miss_st2 && mrvq_full)
|
|
|| (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
|
|
|
|
wire[`LINE_ADDR_WIDTH-1:0] dwbq_req_addr;
|
|
wire dwbq_empty;
|
|
|
|
wire[`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dwbq_req_data;
|
|
|
|
if (SNOOP_FORWARDING_ENABLE) begin
|
|
assign dwbq_req_data = (should_flush && dwbq_push) ? writeword_st2 : readdata_st2;
|
|
assign dwbq_req_addr = (should_flush && dwbq_push) ? addr_st2 : {readtag_st2, addr_st2[`LINE_SELECT_BITS-1:0]};
|
|
end else begin
|
|
assign dwbq_req_data = readdata_st2;
|
|
assign dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_BITS-1:0]};
|
|
end
|
|
|
|
wire possible_fill = valid_st2 && miss_st2 && !dram_fill_req_full && !is_snp_st2;
|
|
wire [`LINE_ADDR_WIDTH-1:0] fill_invalidator_addr = addr_st2;
|
|
|
|
VX_fill_invalidator #(
|
|
.CACHE_SIZE (CACHE_SIZE),
|
|
.BANK_LINE_SIZE (BANK_LINE_SIZE),
|
|
.NUM_BANKS (NUM_BANKS),
|
|
.WORD_SIZE (WORD_SIZE),
|
|
.NUM_REQUESTS (NUM_REQUESTS),
|
|
.STAGE_1_CYCLES (STAGE_1_CYCLES),
|
|
.REQQ_SIZE (REQQ_SIZE),
|
|
.MRVQ_SIZE (MRVQ_SIZE),
|
|
.DFPQ_SIZE (DFPQ_SIZE),
|
|
.SNRQ_SIZE (SNRQ_SIZE),
|
|
.CWBQ_SIZE (CWBQ_SIZE),
|
|
.DWBQ_SIZE (DWBQ_SIZE),
|
|
.DFQQ_SIZE (DFQQ_SIZE),
|
|
.LLVQ_SIZE (LLVQ_SIZE),
|
|
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE)
|
|
) fill_invalidator (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.possible_fill (possible_fill),
|
|
.success_fill (is_fill_st2),
|
|
.fill_addr (fill_invalidator_addr),
|
|
|
|
.invalidate_fill (invalidate_fill)
|
|
);
|
|
|
|
// Enqueue in dram_fill_req
|
|
assign dram_fill_req_valid = possible_fill && !invalidate_fill;
|
|
assign dram_fill_req_is_snp = is_snp_st2 && valid_st2 && miss_st2;
|
|
assign dram_fill_req_addr = addr_st2;
|
|
|
|
assign dram_wb_req_valid = !dwbq_empty;
|
|
|
|
VX_generic_queue #(
|
|
.DATAW(`LINE_ADDR_WIDTH + (`BANK_LINE_WORDS * `WORD_WIDTH)),
|
|
.SIZE(DWBQ_SIZE)
|
|
) dwb_queue (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
|
|
.push (dwbq_push),
|
|
.data_in ({dwbq_req_addr, dwbq_req_data}),
|
|
|
|
.pop (dram_wb_req_pop),
|
|
.data_out({dram_wb_req_addr, dram_wb_req_data}),
|
|
.empty (dwbq_empty),
|
|
.full (dwbq_full)
|
|
);
|
|
|
|
wire snp_fwd_push;
|
|
wire ffsq_empty;
|
|
|
|
assign snp_fwd_push = is_snp_st2
|
|
&& valid_st2
|
|
&& !ffsq_full
|
|
&& !(((valid_st2 && !miss_st2) && cwbq_full)
|
|
|| (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full)
|
|
|| (valid_st2 && miss_st2 && mrvq_full)
|
|
|| (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
|
|
|
|
assign snp_fwd_valid = !ffsq_empty;
|
|
|
|
VX_generic_queue #(
|
|
.DATAW(`LINE_ADDR_WIDTH),
|
|
.SIZE(FFSQ_SIZE)
|
|
) ffs_queue (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.push (snp_fwd_push),
|
|
.data_in (addr_st2),
|
|
.pop (snp_fwd_pop),
|
|
.data_out(snp_fwd_addr),
|
|
.empty (ffsq_empty),
|
|
.full (ffsq_full)
|
|
);
|
|
|
|
assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full)
|
|
|| ((valid_st2 && !miss_st2) && cwbq_full)
|
|
|| (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full)
|
|
|| (valid_st2 && miss_st2 && mrvq_full)
|
|
|| (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full);
|
|
|
|
endmodule : VX_bank |