136 lines
4.9 KiB
Verilog
136 lines
4.9 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache_dram_req_arb #(
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// Size of cache in bytes
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parameter CACHE_SIZE = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Prefetcher
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parameter PRFQ_SIZE = 64,
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parameter PRFQ_STRIDE = 2
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) (
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input wire clk,
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input wire reset,
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// Fill Request
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input wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid,
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input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_fill_req_addr,
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output wire dfqq_full,
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// Writeback Request
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input wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid,
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input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr,
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input wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] per_bank_dram_wb_req_data,
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output wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop,
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// Merged Request
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output wire dram_req_read,
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output wire dram_req_write,
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output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
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input wire dram_req_ready
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);
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wire pref_pop;
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wire pref_valid;
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wire[`DRAM_ADDR_WIDTH-1:0] pref_addr;
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wire dwb_valid;
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wire dfqq_req;
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assign pref_pop = !dwb_valid && !dfqq_req && dram_req_ready && pref_valid;
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VX_prefetcher #(
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.PRFQ_SIZE (PRFQ_SIZE),
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.PRFQ_STRIDE (PRFQ_STRIDE),
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.BANK_LINE_SIZE(BANK_LINE_SIZE),
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.WORD_SIZE (WORD_SIZE)
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) prfqq (
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.clk (clk),
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.reset (reset),
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.dram_req (dram_req_read),
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.dram_req_addr(dram_req_addr),
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.pref_pop (pref_pop),
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.pref_valid (pref_valid),
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.pref_addr (pref_addr)
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);
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wire[`DRAM_ADDR_WIDTH-1:0] dfqq_req_addr;
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`DEBUG_BEGIN
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wire dfqq_empty;
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`DEBUG_END
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wire dfqq_pop = !dwb_valid && dfqq_req && dram_req_ready; // If no dwb, and dfqq has valids, then pop
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wire dfqq_push = (|per_bank_dram_fill_req_valid);
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VX_cache_dfq_queue cache_dfq_queue(
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.clk (clk),
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.reset (reset),
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.dfqq_push (dfqq_push),
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.per_bank_dram_fill_req_valid (per_bank_dram_fill_req_valid),
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.per_bank_dram_fill_req_addr (per_bank_dram_fill_req_addr),
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.dfqq_pop (dfqq_pop),
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.dfqq_req (dfqq_req),
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.dfqq_req_addr (dfqq_req_addr),
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.dfqq_empty (dfqq_empty),
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.dfqq_full (dfqq_full)
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);
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wire [`LOG2UP(NUM_BANKS)-1:0] dwb_bank;
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wire [NUM_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req_valid;
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VX_generic_priority_encoder #(
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.N(NUM_BANKS)
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) sel_dwb (
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.valids(use_wb_valid),
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.index (dwb_bank),
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.found (dwb_valid)
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);
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assign per_bank_dram_wb_queue_pop = dram_req_ready ? (use_wb_valid & ((1 << dwb_bank))) : 0;
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wire dram_req_valid = dwb_valid || dfqq_req || pref_pop;
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assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req_valid;
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assign dram_req_write = dwb_valid && dram_req_valid;
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assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr);
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assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0;
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endmodule |