156 lines
4.0 KiB
Verilog
156 lines
4.0 KiB
Verilog
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`include "VX_define.v"
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module VX_e_m_reg (
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input wire clk,
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input wire[31:0] in_alu_result[`NT_M1:0],
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input wire[4:0] in_rd,
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input wire[1:0] in_wb,
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input wire[4:0] in_rs1,
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input wire[4:0] in_rs2,
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input wire[31:0] in_a_reg_data[`NT_M1:0],
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input wire[31:0] in_b_reg_data[`NT_M1:0],
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input wire[2:0] in_mem_read, // NEW
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input wire[2:0] in_mem_write, // NEW
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input wire[31:0] in_PC_next,
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input wire[11:0] in_csr_address,
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input wire in_is_csr,
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input wire[31:0] in_csr_result,
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input wire[31:0] in_curr_PC,
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input wire[31:0] in_branch_offset,
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input wire[2:0] in_branch_type,
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input wire in_jal,
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input wire[31:0] in_jal_dest,
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input wire in_freeze,
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input wire in_valid[`NT_M1:0],
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output wire[11:0] out_csr_address,
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output wire out_is_csr,
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output wire[31:0] out_csr_result,
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output wire[31:0] out_alu_result[`NT_M1:0],
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output wire[4:0] out_rd,
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output wire[1:0] out_wb,
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output wire[4:0] out_rs1,
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output wire[4:0] out_rs2,
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output wire[31:0] out_a_reg_data[`NT_M1:0],
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output wire[31:0] out_b_reg_data[`NT_M1:0],
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output wire[2:0] out_mem_read,
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output wire[2:0] out_mem_write,
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output wire[31:0] out_curr_PC,
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output wire[31:0] out_branch_offset,
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output wire[2:0] out_branch_type,
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output wire out_jal,
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output wire[31:0] out_jal_dest,
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output wire[31:0] out_PC_next,
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output wire out_valid[`NT_M1:0]
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);
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reg[31:0] alu_result[`NT_M1:0];
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reg[4:0] rd;
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reg[4:0] rs1;
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reg[4:0] rs2;
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reg[31:0] a_reg_data[`NT_M1:0];
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reg[31:0] b_reg_data[`NT_M1:0];
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reg[1:0] wb;
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reg[31:0] PC_next;
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reg[2:0] mem_read;
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reg[2:0] mem_write;
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reg[11:0] csr_address;
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reg is_csr;
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reg[31:0] csr_result;
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reg[31:0] curr_PC;
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reg[31:0] branch_offset;
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reg[2:0] branch_type;
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reg jal;
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reg[31:0] jal_dest;
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reg valid[`NT_M1:0];
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// reg[31:0] reg_data_z[`NT_T2_M1:0];
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// reg[`NT_M1:0] valid_z;
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// reg[31:0] alu_result_z[`NT_M1:0];
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integer ini_reg;
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initial begin
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rd = 0;
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rs1 = 0;
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rs2 = 0;
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wb = 0;
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PC_next = 0;
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mem_read = `NO_MEM_READ;
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mem_write = `NO_MEM_WRITE;
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csr_address = 0;
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is_csr = 0;
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csr_result = 0;
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curr_PC = 0;
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branch_offset = 0;
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branch_type = 0;
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jal = `NO_JUMP;
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jal_dest = 0;
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for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1)
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begin
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a_reg_data[ini_reg] = 0;
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b_reg_data[ini_reg] = 0;
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valid[ini_reg] = 0;
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alu_result[ini_reg] = 0;
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end
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end
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assign out_alu_result = alu_result;
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assign out_rd = rd;
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assign out_rs1 = rs1;
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assign out_rs2 = rs2;
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assign out_wb = wb;
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assign out_PC_next = PC_next;
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assign out_mem_read = mem_read;
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assign out_mem_write = mem_write;
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assign out_a_reg_data = a_reg_data;
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assign out_b_reg_data = b_reg_data;
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assign out_csr_address = csr_address;
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assign out_is_csr = is_csr;
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assign out_csr_result = csr_result;
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assign out_curr_PC = curr_PC;
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assign out_branch_offset = branch_offset;
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assign out_branch_type = branch_type;
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assign out_jal = jal;
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assign out_jal_dest = jal_dest;
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assign out_valid = valid;
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always @(posedge clk) begin
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if(in_freeze == 1'b0) begin
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alu_result <= in_alu_result;
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rd <= in_rd;
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rs1 <= in_rs1;
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rs2 <= in_rs2;
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wb <= in_wb;
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PC_next <= in_PC_next;
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mem_read <= in_mem_read;
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mem_write <= in_mem_write;
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a_reg_data <= in_a_reg_data;
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b_reg_data <= in_b_reg_data;
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csr_address <= in_csr_address;
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is_csr <= in_is_csr;
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csr_result <= in_csr_result;
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curr_PC <= in_curr_PC;
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branch_offset <= in_branch_offset;
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branch_type <= in_branch_type;
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jal <= in_jal;
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jal_dest <= in_jal_dest;
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valid <= in_valid;
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end
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end
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endmodule // VX_e_m_reg
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