447 lines
14 KiB
Systemverilog
447 lines
14 KiB
Systemverilog
`ifndef VX_DEFINE
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`define VX_DEFINE
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`include "VX_platform.vh"
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`include "VX_config.vh"
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`include "VX_scope.vh"
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///////////////////////////////////////////////////////////////////////////////
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// `define SYNTHESIS 1
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// `define ASIC 1
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///////////////////////////////////////////////////////////////////////////////
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`define NW_BITS `LOG2UP(`NUM_WARPS)
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`define NT_BITS `LOG2UP(`NUM_THREADS)
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`define NC_BITS `LOG2UP(`NUM_CORES)
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`define NB_BITS `LOG2UP(`NUM_BARRIERS)
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`define REQS_BITS `LOG2UP(NUM_REQUESTS)
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`ifdef EXT_F_ENABLE
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`define NUM_REGS 64
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`else
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`define NUM_REGS 32
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`endif
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`define NR_BITS `LOG2UP(`NUM_REGS)
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`define CSR_ADDR_BITS 12
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`define CSR_WIDTH 12
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`define ISTAG_BITS `LOG2UP(`ISSUEQ_SIZE)
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///////////////////////////////////////////////////////////////////////////////
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`define LATENCY_IDIV 23
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`define LATENCY_IMUL 2
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`define LATENCY_FDIV 16
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`define LATENCY_FSQRT 10
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`define LATENCY_FTOI 5
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`define LATENCY_FTOU 4
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`define LATENCY_ITOF 8
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`define LATENCY_UTOF 7
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`define LATENCY_FMULADD 2
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`define LATENCY_FDIVSQRT 2
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`define LATENCY_FCONV 2
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`define LATENCY_FNONCOMP 1
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///////////////////////////////////////////////////////////////////////////////
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`define INST_LUI 7'b0110111
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`define INST_AUIPC 7'b0010111
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`define INST_JAL 7'b1101111
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`define INST_JALR 7'b1100111
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`define INST_B 7'b1100011 // branch instructions
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`define INST_L 7'b0000011 // load instructions
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`define INST_S 7'b0100011 // store instructions
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`define INST_I 7'b0010011 // immediate instructions
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`define INST_R 7'b0110011 // register instructions
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`define INST_F 7'b0001111 // Fence instructions
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`define INST_SYS 7'b1110011 // system instructions
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`define INST_FL 7'b0000111 // float load instruction
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`define INST_FS 7'b0100111 // float store instruction
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`define INST_FMADD 7'b1000011
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`define INST_FMSUB 7'b1000111
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`define INST_FNMSUB 7'b1001011
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`define INST_FNMADD 7'b1001111
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`define INST_FCI 7'b1010011 // float common instructions
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`define INST_GPU 7'b1101011
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`define BYTEEN_SB 3'h0
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`define BYTEEN_SH 3'h1
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`define BYTEEN_SW 3'h2
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`define BYTEEN_UB 3'h4
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`define BYTEEN_UH 3'h5
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`define BYTEEN_BITS 3
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`define BYTEEN_TYPE(x) x[1:0]
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`define BR_EQ 4'h0
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`define BR_NE 4'h1
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`define BR_LT 4'h2
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`define BR_GE 4'h3
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`define BR_LTU 4'h4
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`define BR_GEU 4'h5
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`define BR_JAL 4'h6
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`define BR_JALR 4'h7
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`define BR_ECALL 4'h8
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`define BR_EBREAK 4'h9
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`define BR_MRET 4'hA
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`define BR_SRET 4'hB
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`define BR_DRET 4'hC
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`define BR_NO 4'hF
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`define BR_BITS 4
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`define OP_BITS 5
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`define ALU_ADD 5'h00
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`define ALU_SUB 5'h01
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`define ALU_SLL 5'h02
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`define ALU_SRL 5'h03
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`define ALU_SRA 5'h04
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`define ALU_SLT 5'h05
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`define ALU_SLTU 5'h06
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`define ALU_XOR 5'h07
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`define ALU_OR 5'h08
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`define ALU_AND 5'h09
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`define ALU_LUI 5'h0A
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`define ALU_AUIPC 5'h0B
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`define ALU_BEQ {1'b1, `BR_EQ}
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`define ALU_BNE {1'b1, `BR_NE}
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`define ALU_BLT {1'b1, `BR_LT}
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`define ALU_BGE {1'b1, `BR_GE}
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`define ALU_BLTU {1'b1, `BR_LTU}
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`define ALU_BGEU {1'b1, `BR_GEU}
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`define ALU_JAL {1'b1, `BR_JAL}
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`define ALU_JALR {1'b1, `BR_JALR}
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`define ALU_ECALL {1'b1, `BR_ECALL}
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`define ALU_EBREAK {1'b1, `BR_EBREAK}
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`define ALU_MRET {1'b1, `BR_MRET}
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`define ALU_SRET {1'b1, `BR_SRET}
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`define ALU_DRET {1'b1, `BR_DRET}
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`define ALU_OTHER 5'h1F
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`define ALU_BITS 5
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`define ALU_OP(x) x[`ALU_BITS-1:0]
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`define BR_OP(x) x[`BR_BITS-1:0]
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`define IS_BR_OP(x) x[4]
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`define LSU_LB {1'b0, `BYTEEN_SB}
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`define LSU_LH {1'b0, `BYTEEN_SH}
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`define LSU_LW {1'b0, `BYTEEN_SW}
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`define LSU_LBU {1'b0, `BYTEEN_UB}
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`define LSU_LHU {1'b0, `BYTEEN_UH}
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`define LSU_SB {1'b1, `BYTEEN_SB}
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`define LSU_SH {1'b1, `BYTEEN_SH}
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`define LSU_SW {1'b1, `BYTEEN_SW}
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`define LSU_SBU {1'b1, `BYTEEN_UB}
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`define LSU_SHU {1'b1, `BYTEEN_UH}
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`define LSU_BITS 4
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`define LSU_RW(x) x[3]
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`define LSU_BE(x) x[2:0]
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`define CSR_RW 2'h0
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`define CSR_RS 2'h1
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`define CSR_RC 2'h2
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`define CSR_OTHER 2'h3
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`define CSR_BITS 2
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`define CSR_OP(x) x[`CSR_BITS-1:0]
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`define MUL_MUL 3'h0
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`define MUL_MULH 3'h1
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`define MUL_MULHSU 3'h2
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`define MUL_MULHU 3'h3
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`define MUL_DIV 3'h4
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`define MUL_DIVU 3'h5
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`define MUL_REM 3'h6
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`define MUL_REMU 3'h7
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`define MUL_BITS 3
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`define MUL_OP(x) x[`MUL_BITS-1:0]
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`define IS_DIV_OP(x) x[2]
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`define FPU_ADD 5'h00
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`define FPU_SUB 5'h01
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`define FPU_MUL 5'h02
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`define FPU_DIV 5'h03
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`define FPU_SQRT 5'h04
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`define FPU_MADD 5'h05
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`define FPU_MSUB 5'h06
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`define FPU_NMSUB 5'h07
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`define FPU_NMADD 5'h08
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`define FPU_SGNJ 5'h09 // FSGNJ
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`define FPU_SGNJN 5'h0A // FSGNJN
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`define FPU_SGNJX 5'h0B // FSGNJX
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`define FPU_MIN 5'h0C // FMIN.S
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`define FPU_MAX 5'h0D // FMAX.S
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`define FPU_CVTWS 5'h0E // FCVT.W.S
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`define FPU_CVTWUS 5'h0F // FCVT.WU.S
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`define FPU_CVTSW 5'h10 // FCVT.S.W
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`define FPU_CVTSWU 5'h11 // FCVT.S.WU
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`define FPU_MVXW 5'h12 // MOV FP from fpReg to integer reg
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`define FPU_MVWX 5'h13 // MOV FP from integer reg to fpReg
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`define FPU_CLASS 5'h14
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`define FPU_CMP 5'h15
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`define FPU_OTHER 5'h1f
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`define FPU_BITS 5
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`define FPU_OP(x) x[`FPU_BITS-1:0]
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`define FRM_RNE 3'b000 // round to nearest even
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`define FRM_RTZ 3'b001 // round to zero
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`define FRM_RDN 3'b010 // round to -inf
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`define FRM_RUP 3'b011 // round to +inf
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`define FRM_RMM 3'b100 // round to nearest max magnitude
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`define FRM_DYN 3'b111 // dynamic mode
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`define FRM_BITS 3
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`define GPU_TMC 3'h0
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`define GPU_WSPAWN 3'h1
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`define GPU_SPLIT 3'h2
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`define GPU_JOIN 3'h3
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`define GPU_BAR 3'h4
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`define GPU_OTHER 3'h7
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`define GPU_BITS 3
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`define GPU_OP(x) x[`GPU_BITS-1:0]
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`define EX_NOP 3'h0
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`define EX_ALU 3'h1
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`define EX_LSU 3'h2
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`define EX_CSR 3'h3
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`define EX_MUL 3'h4
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`define EX_FPU 3'h5
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`define EX_GPU 3'h6
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`define EX_BITS 3
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`define NUM_EXS 6
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`define NE_BITS `LOG2UP(`NUM_EXS)
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///////////////////////////////////////////////////////////////////////////////
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`ifdef EXT_M_ENABLE
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`define ISA_EXT_M (1 << 12)
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`else
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`define ISA_EXT_M 0
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`endif
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`ifdef EXT_F_ENABLE
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`define ISA_EXT_F (1 << 5)
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`else
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`define ISA_EXT_F 0
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`endif
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`define ISA_CODE (0 << 0) // A - Atomic Instructions extension \
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| (0 << 1) // B - Tentatively reserved for Bit operations extension \
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| (0 << 2) // C - Compressed extension \
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| (0 << 3) // D - Double precsision floating-point extension \
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| (0 << 4) // E - RV32E base ISA \
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|`ISA_EXT_F // F - Single precsision floating-point extension \
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| (0 << 6) // G - Additional standard extensions present \
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| (0 << 7) // H - Hypervisor mode implemented \
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| (1 << 8) // I - RV32I/64I/128I base ISA \
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| (0 << 9) // J - Reserved \
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| (0 << 10) // K - Reserved \
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| (0 << 11) // L - Tentatively reserved for Bit operations extension \
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|`ISA_EXT_M // M - Integer Multiply/Divide extension \
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| (0 << 13) // N - User level interrupts supported \
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| (0 << 14) // O - Reserved \
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| (0 << 15) // P - Tentatively reserved for Packed-SIMD extension \
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| (0 << 16) // Q - Quad-precision floating-point extension \
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| (0 << 17) // R - Reserved \
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| (0 << 18) // S - Supervisor mode implemented \
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| (0 << 19) // T - Tentatively reserved for Transactional Memory extension \
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| (1 << 20) // U - User mode implemented \
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| (0 << 21) // V - Tentatively reserved for Vector extension \
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| (0 << 22) // W - Reserved \
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| (1 << 23) // X - Non-standard extensions present \
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| (0 << 24) // Y - Reserved \
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| (0 << 25) // Z - Reserved
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///////////////////////////////////////////////////////////////////////////////
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`ifdef DBG_CORE_REQ_INFO // pc, wb, rd, warp_num
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`define DEBUG_CORE_REQ_MDATA_WIDTH (32 + 1 + `NR_BITS + `NW_BITS)
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`else
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`define DEBUG_CORE_REQ_MDATA_WIDTH 0
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`endif
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////////////////////////// Dcache Configurable Knobs //////////////////////////
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// Cache ID
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`define DCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 0)
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// TAG sharing enable
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`define DCORE_TAG_ID_BITS `ISTAG_BITS
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// Core request tag bits
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`define DCORE_TAG_WIDTH (`DEBUG_CORE_REQ_MDATA_WIDTH + `DCORE_TAG_ID_BITS)
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// DRAM request data bits
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`define DDRAM_LINE_WIDTH (`DBANK_LINE_SIZE * 8)
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// DRAM request address bits
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`define DDRAM_ADDR_WIDTH (32 - `CLOG2(`DBANK_LINE_SIZE))
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// DRAM byte enable bits
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`define DDRAM_BYTEEN_WIDTH `DBANK_LINE_SIZE
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// DRAM request tag bits
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`define DDRAM_TAG_WIDTH `DDRAM_ADDR_WIDTH
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define DNUM_REQUESTS `NUM_THREADS
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// Snoop request tag bits
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`define DSNP_TAG_WIDTH ((`NUM_CORES > 1) ? `LOG2UP(`L2SNRQ_SIZE) : `L2SNP_TAG_WIDTH)
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////////////////////////// Icache Configurable Knobs //////////////////////////
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// Cache ID
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`define ICACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 1)
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// Core request address bits
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`define ICORE_ADDR_WIDTH (32-`CLOG2(`IWORD_SIZE))
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// Core request byte enable bits
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`define ICORE_BYTEEN_WIDTH `DWORD_SIZE
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// TAG sharing enable
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`define ICORE_TAG_ID_BITS `NW_BITS
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// Core request tag bits
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`define ICORE_TAG_WIDTH (`DEBUG_CORE_REQ_MDATA_WIDTH + `ICORE_TAG_ID_BITS)
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// DRAM request data bits
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`define IDRAM_LINE_WIDTH (`IBANK_LINE_SIZE * 8)
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// DRAM request address bits
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`define IDRAM_ADDR_WIDTH (32 - `CLOG2(`IBANK_LINE_SIZE))
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// DRAM byte enable bits
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`define IDRAM_BYTEEN_WIDTH `IBANK_LINE_SIZE
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// DRAM request tag bits
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`define IDRAM_TAG_WIDTH `IDRAM_ADDR_WIDTH
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define INUM_REQUESTS 1
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////////////////////////// SM Configurable Knobs //////////////////////////////
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// Cache ID
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`define SCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 2)
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define SNUM_REQUESTS `NUM_THREADS
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// DRAM request address bits
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`define SDRAM_ADDR_WIDTH (32 - `CLOG2(`SBANK_LINE_SIZE))
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// DRAM request tag bits
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`define SDRAM_TAG_WIDTH `SDRAM_ADDR_WIDTH
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define SNUM_REQUESTS `NUM_THREADS
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////////////////////////// L2cache Configurable Knobs /////////////////////////
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// Cache ID
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`define L2CACHE_ID (`L3_ENABLE ? 1 : 0)
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// Core request tag bits
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`define L2CORE_TAG_WIDTH (`DCORE_TAG_WIDTH + `CLOG2(`NUM_CORES))
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// DRAM request data bits
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`define L2DRAM_LINE_WIDTH (`L2_ENABLE ? (`L2BANK_LINE_SIZE * 8) : `DDRAM_LINE_WIDTH)
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// DRAM request address bits
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`define L2DRAM_ADDR_WIDTH (`L2_ENABLE ? (32 - `CLOG2(`L2BANK_LINE_SIZE)) : `DDRAM_ADDR_WIDTH)
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// DRAM byte enable bits
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`define L2DRAM_BYTEEN_WIDTH (`L2_ENABLE ? `L2BANK_LINE_SIZE : `DDRAM_BYTEEN_WIDTH)
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// DRAM request tag bits
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`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `L2DRAM_ADDR_WIDTH : (`L2DRAM_ADDR_WIDTH+`CLOG2(`NUM_CORES*2)))
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// Snoop request tag bits
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`define L2SNP_TAG_WIDTH (`L3_ENABLE ? `LOG2UP(`L3SNRQ_SIZE) : `L3SNP_TAG_WIDTH)
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define L2NUM_REQUESTS (2 * `NUM_CORES)
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////////////////////////// L3cache Configurable Knobs /////////////////////////
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// Cache ID
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`define L3CACHE_ID 0
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// Core request tag bits
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`define L3CORE_TAG_WIDTH (`L2CORE_TAG_WIDTH + `CLOG2(`NUM_CLUSTERS))
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// DRAM request data bits
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`define L3DRAM_LINE_WIDTH (`L3_ENABLE ? (`L3BANK_LINE_SIZE * 8) : `L2DRAM_LINE_WIDTH)
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// DRAM request address bits
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`define L3DRAM_ADDR_WIDTH (`L3_ENABLE ? (32 - `CLOG2(`L3BANK_LINE_SIZE)) : `L2DRAM_ADDR_WIDTH)
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// DRAM byte enable bits
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`define L3DRAM_BYTEEN_WIDTH (`L3_ENABLE ? `L3BANK_LINE_SIZE : `L2DRAM_BYTEEN_WIDTH)
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// DRAM request tag bits
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`define L3DRAM_TAG_WIDTH (`L3_ENABLE ? `L3DRAM_ADDR_WIDTH : `L2DRAM_TAG_WIDTH)
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// Snoop request tag bits
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`define L3SNP_TAG_WIDTH 16
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define L3NUM_REQUESTS `NUM_CLUSTERS
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///////////////////////////////////////////////////////////////////////////////
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`define VX_DRAM_BYTEEN_WIDTH `L3DRAM_BYTEEN_WIDTH
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`define VX_DRAM_ADDR_WIDTH `L3DRAM_ADDR_WIDTH
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`define VX_DRAM_LINE_WIDTH `L3DRAM_LINE_WIDTH
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`define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH
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`define VX_SNP_TAG_WIDTH `L3SNP_TAG_WIDTH
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`define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH
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`define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES)
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`define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)}
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///////////////////////////////////////////////////////////////////////////////
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typedef struct packed {
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logic [`NW_BITS-1:0] warp_num;
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logic [`NUM_THREADS-1:0] thread_mask;
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logic [31:0] curr_PC;
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logic [`NR_BITS-1:0] rd;
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logic wb;
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} issue_data_t;
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typedef struct packed {
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logic is_normal;
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logic is_zero;
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logic is_subnormal;
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logic is_inf;
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logic is_nan;
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logic is_signaling;
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logic is_quiet;
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} fp_type_t;
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typedef struct packed {
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logic NV; // Invalid
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logic DZ; // Divide by zero
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logic OF; // Overflow
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logic UF; // Underflow
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logic NX; // Inexact
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} fflags_t;
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`define FFG_BITS $bits(fflags_t)
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`endif
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