85 lines
3.7 KiB
Verilog
85 lines
3.7 KiB
Verilog
`include "VX_define.vh"
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module VX_scheduler #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_decode_if decode_if,
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VX_wb_if writeback_if,
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VX_cmt_to_issue_if cmt_to_issue_if,
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input wire ex_busy,
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input wire gpr_busy,
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output wire [`ISTAG_BITS-1:0] issue_tag,
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output wire schedule_delay
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);
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localparam CTVW = `CLOG2(`NUM_WARPS * `NUM_REGS + 1);
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reg [`NUM_THREADS-1:0] inuse_registers [(`NUM_WARPS * `NUM_REGS)-1:0];
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reg [`NUM_REGS-1:0] inuse_reg_mask [`NUM_WARPS-1:0];
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wire [`NUM_REGS-1:0] inuse_mask = inuse_reg_mask[decode_if.warp_num] & decode_if.reg_use_mask;
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wire inuse_hazard = (inuse_mask != 0);
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wire issue_buf_full;
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wire stall = gpr_busy || ex_busy || inuse_hazard || issue_buf_full;
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wire issue_fire = decode_if.valid && ~stall;
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wire acquire_rd = issue_fire && (decode_if.wb != 0);
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wire release_rd = writeback_if.valid;
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wire [`NUM_THREADS-1:0] inuse_registers_n = inuse_registers[{writeback_if.warp_num, writeback_if.rd}] & ~writeback_if.thread_mask;
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always @(posedge clk) begin
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if (reset) begin
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for (integer w = 0; w < `NUM_WARPS; w++) begin
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for (integer i = 0; i < `NUM_REGS; i++) begin
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inuse_registers[w * `NUM_REGS + i] <= 0;
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end
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inuse_reg_mask[w] <= `NUM_REGS'(0);
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end
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end else begin
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if (acquire_rd) begin
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inuse_registers[{decode_if.warp_num, decode_if.rd}] <= decode_if.thread_mask;
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inuse_reg_mask[decode_if.warp_num][decode_if.rd] <= 1;
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end
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if (release_rd) begin
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assert(inuse_reg_mask[writeback_if.warp_num][writeback_if.rd] != 0);
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inuse_registers[{writeback_if.warp_num, writeback_if.rd}] <= inuse_registers_n;
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inuse_reg_mask[writeback_if.warp_num][writeback_if.rd] <= (| inuse_registers_n);
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end
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end
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end
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VX_cam_buffer #(
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.DATAW ($bits(issue_data_t)),
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.SIZE (`ISSUEQ_SIZE),
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.RPORTS (`NUM_EXS)
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) issue_buffer (
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.clk (clk),
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.reset (reset),
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.write_data ({decode_if.warp_num, decode_if.thread_mask, decode_if.curr_PC, decode_if.rd, decode_if.wb}),
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.write_addr (issue_tag),
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.acquire_slot (issue_fire),
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.release_slot ({cmt_to_issue_if.alu_valid, cmt_to_issue_if.lsu_valid, cmt_to_issue_if.csr_valid, cmt_to_issue_if.mul_valid, cmt_to_issue_if.fpu_valid, cmt_to_issue_if.gpu_valid}),
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.read_addr ({cmt_to_issue_if.alu_tag, cmt_to_issue_if.lsu_tag, cmt_to_issue_if.csr_tag, cmt_to_issue_if.mul_tag, cmt_to_issue_if.fpu_tag, cmt_to_issue_if.gpu_tag}),
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.read_data ({cmt_to_issue_if.alu_data, cmt_to_issue_if.lsu_data, cmt_to_issue_if.csr_data, cmt_to_issue_if.mul_data, cmt_to_issue_if.fpu_data, cmt_to_issue_if.gpu_data}),
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.full (issue_buf_full)
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);
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assign schedule_delay = stall;
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (decode_if.valid && stall) begin
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$display("%t: Core%0d-stall: warp=%0d, PC=%0h, rd=%0d, wb=%0d, ib_full=%b, inuse=%b%b%b%b, ex_busy=%b, gpr_busy=%b",
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$time, CORE_ID, decode_if.warp_num, decode_if.curr_PC, decode_if.rd, decode_if.wb, issue_buf_full,
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inuse_mask[decode_if.rd], inuse_mask[decode_if.rs1], inuse_mask[decode_if.rs2], inuse_mask[decode_if.rs3], ex_busy, gpr_busy);
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end
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end
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`endif
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endmodule |