Blaise Tine fceb561cbd synchronous reset network optimization: only reset register when required

2020-11-11 20:54:54 -08:00

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VX_bank_core_req_arb.v

fixed bank_core_req_abr critical path

2020-11-08 18:25:32 -08:00

VX_bank.v

fixed redundant cache fills

2020-11-11 12:07:27 -05:00

VX_cache_config.vh

scope refactoring

2020-10-03 18:53:21 -04:00

VX_cache_core_req_bank_sel.v

refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2

2020-11-08 01:31:46 -08:00

VX_cache_core_rsp_merge.v

fixed cache_core_rsp_merge unit

2020-11-09 02:10:35 -08:00

VX_cache_dram_req_arb.v

refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2

2020-11-08 01:31:46 -08:00

VX_cache_miss_resrv.v

fixed DRAM response backpressure inside Cache

2020-11-10 05:24:57 -08:00

VX_cache.v

synchronous reset network optimization: only reset register when required

2020-11-11 20:54:54 -08:00

VX_data_access.v

refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2

2020-11-08 01:31:46 -08:00

VX_data_store.v

cache refactoring - phase 3 - added dedicated pipeline stage for tag access

2020-11-04 03:21:30 -08:00

VX_snp_forwarder.v

fixed DRAM response backpressure inside Cache

2020-11-10 05:24:57 -08:00

VX_snp_rsp_arb.v

fixed snoop forwarding hang

2020-11-09 20:02:33 -08:00

VX_tag_access.v

fixed redundant cache fills

2020-11-11 12:07:27 -05:00

VX_tag_store.v

fixed redundnat cache fill with dirty block, fixed cache tag_store critical path

2020-11-10 08:32:34 -08:00