felsabbagh3 fd876144f5 .tcl mod

2019-10-21 11:27:01 -04:00

..

191017.log

added log file

2019-10-17 14:00:22 -04:00

dc.log

Added log file of synthesis, too many registers are removed

2019-10-17 14:25:54 -04:00

syn.tcl

.tcl mod

2019-10-21 11:27:01 -04:00