38 lines
450 B
Verilog
38 lines
450 B
Verilog
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`ifndef VX_WB_INTER
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`define VX_WB_INTER
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interface VX_wb_inter ();
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wire[`NT_M1:0][31:0] write_data;
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wire[4:0] rd;
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wire[1:0] wb;
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wire[`NT_M1:0] wb_valid;
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wire[`NW_M1:0] wb_warp_num;
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modport snk (
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input write_data,
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input rd,
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input wb,
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input wb_valid,
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input wb_warp_num
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);
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modport src (
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output write_data,
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output rd,
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output wb,
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output wb_valid,
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output wb_warp_num
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);
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endinterface
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`endif |