Blaise Tine b14825c8b9 update fpga build settings

2021-06-04 20:45:56 -07:00

..

modelsim

code refactoring: DRAM => MEM renaming

2021-04-26 00:58:48 -07:00

opae

update fpga build settings

2021-06-04 20:45:56 -07:00

quartus

adding synthesis build for shared memory

2021-05-25 22:02:42 -07:00

synopsys

fix opae build

2020-04-20 12:51:42 -07:00

yosys

scope refactoring: adding modules definitions to VCD trace

2020-10-12 23:26:02 -04:00