From 09d9d3c3f968cd5458ece2f35d9d074d86b3bd97 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Sat, 25 May 2024 20:13:56 -0700
Subject: [PATCH] Bump vortex with multi-warp tensor core fix

---
 src/main/resources/vsrc/vortex                   | 2 +-
 src/main/scala/radiance/memory/VortexCache.scala | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex
index 45d86b2..864265b 160000
--- a/src/main/resources/vsrc/vortex
+++ b/src/main/resources/vsrc/vortex
@@ -1 +1 @@
-Subproject commit 45d86b26a2d32f6fdec33ec9a9be5df1f850f057
+Subproject commit 864265bda5ee5115d0de15939ea59ba92145295b
diff --git a/src/main/scala/radiance/memory/VortexCache.scala b/src/main/scala/radiance/memory/VortexCache.scala
index 24c7bb7..f1eb158 100644
--- a/src/main/scala/radiance/memory/VortexCache.scala
+++ b/src/main/scala/radiance/memory/VortexCache.scala
@@ -127,7 +127,9 @@ class VortexBankPassThrough(config: VortexL1Config)(implicit p: Parameters)
     // hack due to not doing proper param negotiations across disconnected
     // Diplomacy graphs.
     // println(s"${upstream.params.sourceBits} <= ${downstream.params.sourceBits}")
-    require(upstream.params.sourceBits <= downstream.params.sourceBits)
+    require(upstream.params.sourceBits <= downstream.params.sourceBits,
+            "mem-side source of L1 cache truncates core-side source! " +
+            "Try lowering core or coalescer srcIds")
 
     downstream.a <> upstream.a
     upstream.d <> downstream.d