add synthesized printf for print buffer

src/main/scala/radiance/memory/Coalescing.scala

@@ -625,6 +625,7 @@ class MonoCoalescer(
   }
 
   // debug prints
+  /*
   when(leadersValid.reduce(_ || _)) {
     matchCounts.zipWithIndex.foreach { case (count, i) =>
       printf(s"lane[${i}] matchCount = %d\n", count);
@@ -639,6 +640,7 @@ class MonoCoalescer(
     hits.foreach { m => printf("%d ", m) }
     printf("]\n")
   }
+  */
 
   io.results.leaderIdx := chosenLeaderIdx
   io.results.baseAddr := chosenLeader.address & addrMask
@@ -711,7 +713,7 @@ class MultiCoalescer(
   when(normalizedMatches.map(_ > 1.U).reduce(_ || _)) {
     chosenSizeIdx := argMax(normalizedMatches)
     chosenValid := true.B
-    printf("coalescing success by matches policy\n")
+    // printf("coalescing success by matches policy\n")
   }.otherwise {
     chosenSizeIdx := DontCare
     chosenValid := false.B
@@ -1371,12 +1373,12 @@ class InFlightTable(
         (laneEntry.reqs zip laneInv.asBools).zipWithIndex
           .foreach { case ((reqEntry, inv), i) =>
             val req = io.windowElts(lane)(i)
-            when((io.invalidate.valid && inv)) {
+            /* when((io.invalidate.valid && inv)) {
               printf(
                 s"coalescer: reqQueue($lane)($i) got invalidated (source=%d)\n",
                 req.source
               )
-            }
+            } */
             reqEntry.valid := (io.invalidate.valid && inv)
             reqEntry.op := req.op
             reqEntry.source := req.source

src/main/scala/radiance/tile/RadianceCluster.scala

@@ -11,6 +11,7 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.TraceBundle
 import freechips.rocketchip.tilelink._
 import gemmini._
+import midas.targetutils.SynthesizePrintf
 import org.chipsalliance.cde.config.Parameters
 import radiance.memory._
 
@@ -329,12 +330,12 @@ class RadianceCluster (
   (radianceAccSlaveNodes zip radianceTiles).foreach { case (a, r) => a := r.accMasterNode }
   val gemminiAccMasterNode = AccMasterNode()
   gemminiTile.accSlaveNode := gemminiAccMasterNode
-
   gemminiTile.slaveNode :=* TLWidthWidget(4) :=* clbus.outwardNode
 
-  assert(smem_size == 0x4000, "fix me")
+  val traceTLNode = TLAdapterNode(clientFn = c => c, managerFn = m => m)
   // printf and perf counter buffer
-  TLRAM(AddressSet(x"ff000000" + smem_size, numCores * 0x200 - 1)) := TLFragmenter(4, 4) := clbus.outwardNode
+  TLRAM(AddressSet(x"ff000000" + smem_size, numCores * 0x200 - 1)) := traceTLNode := TLFragmenter(4, 4) := clbus.outwardNode
+
 
   // Diplomacy sink nodes for cluster-wide barrier sync signal
   val barrierSlaveNode = BarrierSlaveNode(numCores)
@@ -356,20 +357,6 @@ class RadianceCluster (
   }
   // perSmemPortXbars.foreach { clbus.inwardNode := _.node }
 
-  // Memory-mapped register for barrier sync
-  val regDevice = new SimpleDevice("radiance-cluster-barrier-reg",
-                                   Seq(s"radiance-cluster-barrier-reg${clusterId}"))
-  val regNode = TLRegisterNode(
-    address = Seq(AddressSet(0xff004f00L, 0xff)),
-    device = regDevice,
-    beatBytes = wordSize,
-    concurrency = 1)
-  regNode := clbus.outwardNode
-
-  nodes.foreach({ node =>
-      println(s"======= RadianceCluster node.name: ${node.name}")
-  })
-
   override lazy val module = new RadianceClusterModuleImp(this)
 }
 
@@ -399,6 +386,16 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp(
   outer.radianceAccSlaveNodes.foreach(_.in.head._1.status := gemminiAcc.status)
   gemminiAcc.cmd := coreAcc.cmd
 
+  (outer.traceTLNode.in.map(_._1) zip outer.traceTLNode.out.map(_._1)).foreach { case (i, o) =>
+    o.a <> i.a
+    i.d <> o.d
+
+    when (i.a.fire) {
+      when (i.a.bits.opcode === TLMessages.PutFullData || i.a.bits.opcode === TLMessages.PutPartialData) {
+        SynthesizePrintf(printf(s"TRACEWR ${outer.traceTLNode.name}: %x %x %x\n", i.a.bits.address, i.a.bits.data, i.a.bits.mask))
+      }
+    }
+  }
 
   // TODO: remove Pipeline dependency of gemmini
   def makeSmemBanks(): Unit = {