From 24f4ee93accf17fd91a503662a43a352eb1ccccc Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Mon, 27 Feb 2023 23:35:14 -0800
Subject: [PATCH] Add TL client node to MemTraceDriver

---
 src/main/scala/tilelink/Coalescing.scala | 51 ++++++++++++++----------
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 0278384..5ae1475 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -8,14 +8,15 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.unittest._
 
-class CoalescingUnit(txns: Int = 5000)(implicit p: Parameters) extends LazyModule {
+class CoalescingUnit(txns: Int = 5000)(implicit p: Parameters)
+    extends LazyModule {
   val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("Xbar"))
   val xbar = LazyModule(new TLXbar)
 
   xbar.node := TLDelayer(0.1) := model.node := fuzz.node
   (0 until 1) foreach { n =>
-    val ram  = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
+    val ram = LazyModule(new TLRAM(AddressSet(0x0 + 0x400 * n, 0x3ff)))
     ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
   }
 
@@ -25,20 +26,31 @@ class CoalescingUnit(txns: Int = 5000)(implicit p: Parameters) extends LazyModul
   }
 }
 
-class MemTraceDriver(implicit p: Parameters) extends Module with UnitTestModule {
-  val sim = Module(new SimMemTrace)
-  sim.io.clock := clock
-  sim.io.reset := reset.asBool
-  sim.io.trace_read.ready := true.B
-
-  when (sim.io.trace_read.valid) {
-    println("sim.io.valid!")
-  }
-
+class MemTraceDriver(implicit p: Parameters) extends LazyModule {
   // TODO: generate TL request here
+  // testchipip provides TLHelper.makeClientNode convenience wrapper for this.
+  val clients = Seq(
+    TLMasterParameters.v1(
+      name = "MemTraceDriver",
+      sourceId = IdRange(0, 1 /*FIXME*/ )
+    )
+  )
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(clients)))
 
-  // we're finished when there is no more memtrace to read
-  io.finished := !sim.io.trace_read.valid
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) with UnitTestModule {
+    val sim = Module(new SimMemTrace)
+    sim.io.clock := clock
+    sim.io.reset := reset.asBool
+    sim.io.trace_read.ready := true.B
+
+    when(sim.io.trace_read.valid) {
+      println("sim.io.valid!")
+    }
+
+    // we're finished when there is no more memtrace to read
+    io.finished := !sim.io.trace_read.valid
+  }
 }
 
 class SimMemTrace extends BlackBox with HasBlackBoxResource {
@@ -58,12 +70,11 @@ class SimMemTrace extends BlackBox with HasBlackBoxResource {
   addResource("/csrc/SimMemTrace.cc")
 }
 
-class CoalescingUnitTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters)
-extends UnitTest(timeout) {
-  // val dut = Module(LazyModule(new CoalescingUnit(txns)).module)
-  // dut.io.start := io.start
-
-  val driver = Module(new MemTraceDriver)
+class CoalescingUnitTest(txns: Int = 5000, timeout: Int = 500000)(implicit
+    p: Parameters
+) extends UnitTest(timeout) {
+  val coal = Module(LazyModule(new CoalescingUnit(txns)).module)
+  val driver = Module(LazyModule(new MemTraceDriver).module)
   driver.io.start := io.start
 
   io.finished := driver.io.finished