From 2ca2ee37b0fffeb7225940b03c206f3237f10b85 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 15 Oct 2024 15:45:59 -0700 Subject: [PATCH] tensor: Fix writeback datawidth --- src/main/scala/radiance/core/TensorCoreDecoupled.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/radiance/core/TensorCoreDecoupled.scala b/src/main/scala/radiance/core/TensorCoreDecoupled.scala index 617659d..65246f6 100644 --- a/src/main/scala/radiance/core/TensorCoreDecoupled.scala +++ b/src/main/scala/radiance/core/TensorCoreDecoupled.scala @@ -42,7 +42,7 @@ class TensorCoreDecoupled( val writeback = Decoupled(new Bundle { val last = Bool() val wid = UInt(numWarpBits.W) - val data = Vec(numLanes, UInt(wordSize.W)) + val data = Vec(numLanes, UInt((wordSize * 8/*bits*/).W)) }) val respA = Flipped(Decoupled(new TensorMemResp(sourceWidth, dataWidth))) val respB = Flipped(Decoupled(new TensorMemResp(sourceWidth, dataWidth))) @@ -135,7 +135,7 @@ class TensorCoreDecoupled( // Execute stage // ------------- - // Execute backend of the decoupled access/execute pipeline. + // Backend of the decoupled access/execute pipeline. // val respQueueDepth = 4 // FIXME: parameterize val respQueueA = Queue(io.respA, respQueueDepth) @@ -144,7 +144,7 @@ class TensorCoreDecoupled( respQueueB.ready := io.writeback.ready // FIXME require(respQueueA.bits.data.widthOption.get == - io.writeback.bits.data.widthOption.get * numLanes, + io.writeback.bits.data.widthOption.get, "response data width does not match the writeback data width") // FIXME: debug dummy: pipe A directly to writeback