From 2d6bf7dd45b64fe9a934f76d4091f91597c5924a Mon Sep 17 00:00:00 2001 From: Zhongdi LUO Date: Mon, 13 Jul 2026 07:48:00 +0000 Subject: [PATCH] fix: configure tensor DPU precision by architecture --- radiance.mk | 6 +++--- src/main/resources/vsrc/vortex | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/radiance.mk b/radiance.mk index 11bbf42..08a7ce6 100644 --- a/radiance.mk +++ b/radiance.mk @@ -18,13 +18,13 @@ ifeq ($(shell echo $(CONFIG) | grep -E "SynConfig$$"),$(CONFIG)) EXTRA_SIM_PREPROC_DEFINES += +define+SYNTHESIS +define+NDEBUG +define+DPI_DISABLE endif ifeq ($(shell echo $(CONFIG) | grep -E "(FP16|Volta|Ampere)Config$$"),$(CONFIG)) - EXTRA_SIM_PREPROC_DEFINES += +define+NUM_CORES=1 + EXTRA_SIM_PREPROC_DEFINES += +define+NUM_CORES=1 +define+TENSOR_DPU_FP16 endif ifeq ($(shell echo $(CONFIG) | grep -E "HopperConfig$$"),$(CONFIG)) - EXTRA_SIM_PREPROC_DEFINES += +define+NUM_CORES=1 +define+EXT_T_HOPPER + EXTRA_SIM_PREPROC_DEFINES += +define+NUM_CORES=1 +define+EXT_T_HOPPER +define+TENSOR_DPU_FP16 endif ifeq ($(shell echo $(CONFIG) | grep -E "BlackwellConfig$$"),$(CONFIG)) - EXTRA_SIM_PREPROC_DEFINES += +define+NUM_CORES=1 +define+EXT_T_BLACKWELL + EXTRA_SIM_PREPROC_DEFINES += +define+NUM_CORES=1 +define+EXT_T_BLACKWELL +define+TENSOR_DPU_FP16 endif ifeq ($(shell echo $(CONFIG) | grep -E "FlashConfig$$"),$(CONFIG)) EXTRA_SIM_PREPROC_DEFINES += +define+NUM_CORES=4 diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex index fb56e62..4ec2099 160000 --- a/src/main/resources/vsrc/vortex +++ b/src/main/resources/vsrc/vortex @@ -1 +1 @@ -Subproject commit fb56e625bb8dcf5397727d6789b10cc28644677b +Subproject commit 4ec20991067de3adf19fba5ae3109a1a2358e78f