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refactor smem counter

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This commit is contained in:
Richard Yan
2024-09-24 17:24:52 -07:00
parent 85336399c2
commit 3b8c9812b4
3 changed files with 10 additions and 25 deletions
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3
src/main/scala/radiance/tile/RadianceCluster.scala
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@@ -35,7 +35,6 @@ class RadianceCluster (
// Instantiate cluster-local shared memory scratchpad // Instantiate cluster-local shared memory scratchpad
// //
// Instantiate the same number of banks as there are lanes. // Instantiate the same number of banks as there are lanes.
// val numLsuLanes = 4 // FIXME: hardcoded
// must toSeq here, otherwise Iterable is lazy and will break diplomacy // must toSeq here, otherwise Iterable is lazy and will break diplomacy
val gemminiTiles = leafTiles.values.filter(_.isInstanceOf[GemminiTile]).toSeq.asInstanceOf[Seq[GemminiTile]] val gemminiTiles = leafTiles.values.filter(_.isInstanceOf[GemminiTile]).toSeq.asInstanceOf[Seq[GemminiTile]]
@@ -43,7 +42,7 @@ class RadianceCluster (
// TODO: this probably needs to be instantiated inside the radiance shared mem module // TODO: this probably needs to be instantiated inside the radiance shared mem module
val virgoSharedMemComponents = new VirgoSharedMemComponents(thisClusterParams, gemminiTiles, radianceTiles) val virgoSharedMemComponents = new VirgoSharedMemComponents(thisClusterParams, gemminiTiles, radianceTiles)
lazy val sharedMemSystem = LazyModule(new RadianceSharedMem(virgoSharedMemComponents, clbus)) val sharedMemSystem = LazyModule(new RadianceSharedMem(virgoSharedMemComponents, clbus))
val numCoresInCluster = leafTiles.size - gemminiTiles.size val numCoresInCluster = leafTiles.size - gemminiTiles.size

30
src/main/scala/radiance/tile/RadianceSharedMem.scala
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@@ -248,23 +248,14 @@ class RadianceSharedMemImp(outer: RadianceSharedMem) extends LazyModuleImp(outer
wNode.d <> Queue(writeResp, 2) wNode.d <> Queue(writeResp, 2)
} }
// read/write access counter for smem banks
// TODO: simplify wire initialization and use tree reduction val Seq(smemReadsPerCycle, smemWritesPerCycle) = outer.smemBankMgrs.transpose.map { rw =>
// read OR write access counter for smem banks VecInit(rw.map(_.in.head._1.a.fire.asUInt)).reduceTree(_ +& _)
val smemBankMgrsGrouped = outer.smemBankMgrs.grouped(outer.smemSubbanks) }
val numBanks = smemBankMgrsGrouped.length val smemReadCounter = RegInit(0.U(32.W))
val counterWidth = 32 val smemWriteCounter = RegInit(0.U(32.W))
val smemReadsPerBankPerCycle = Seq.fill(numBanks)(Seq.fill(outer.smemSubbanks) smemReadCounter := smemReadCounter +& smemReadsPerCycle
(Wire(UInt(counterWidth.W)))) smemWriteCounter := smemWriteCounter +& smemWritesPerCycle
val smemWritesPerBankPerCycle = Seq.fill(numBanks)(Seq.fill(outer.smemSubbanks)
(Wire(UInt(counterWidth.W))))
val smemReadsPerCycle = smemReadsPerBankPerCycle.map(_.reduce(_ + _)).reduce(_ + _)
val smemWritesPerCycle = smemWritesPerBankPerCycle.map(_.reduce(_ + _)).reduce(_ + _)
val smemReadCounter = RegInit(UInt(counterWidth.W), 0.U)
val smemWriteCounter = RegInit(UInt(counterWidth.W), 0.U)
smemReadCounter := smemReadCounter + smemReadsPerCycle
smemWriteCounter := smemWriteCounter + smemWritesPerCycle
// smemReadsPerBankPerCycle.foreach(_.foreach(dontTouch(_)))
dontTouch(smemReadCounter) dontTouch(smemReadCounter)
dontTouch(smemWriteCounter) dontTouch(smemWriteCounter)
@@ -315,11 +306,6 @@ class RadianceSharedMemImp(outer: RadianceSharedMem) extends LazyModuleImp(outer
makeBuffer(mem, rNode, rEdge, wNode, wEdge) makeBuffer(mem, rNode, rEdge, wNode, wEdge)
// TODO: these should also work for non-stride-by-word
// add access counters to banks
smemReadsPerBankPerCycle(bid)(wid) := (rNode.a.fire === true.B)
smemWritesPerBankPerCycle(bid)(wid) := (wNode.a.fire === true.B)
(uniformFires zip outer.uniformNodesOut).foreach { case (uf, n) => (uniformFires zip outer.uniformNodesOut).foreach { case (uf, n) =>
uf(bid)(wid) := n(bid)(wid).in.head._1.a.fire uf(bid)(wid) := n(bid)(wid).in.head._1.a.fire
} }

2
src/main/scala/radiance/tile/VirgoSharedMemComponents.scala
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@@ -31,7 +31,7 @@ class VirgoSharedMemComponents(
val gemminis = gemminiTiles.map(_.gemmini) val gemminis = gemminiTiles.map(_.gemmini)
val gemminiConfigs = gemminis.map(_.config) val gemminiConfigs = gemminis.map(_.config)
gemminiConfigs.foreach { config => gemminiConfigs.foreach { config =>
assert(smemBanks == config.sp_banks && isPow2(smemBanks / config.sp_banks)) // TODO: should allow >= assert(smemBanks == config.sp_banks && isPow2(smemBanks / config.sp_banks))
assert(smemWidth >= (config.sp_width / 8) && isPow2(smemWidth / (config.sp_width / 8))) assert(smemWidth >= (config.sp_width / 8) && isPow2(smemWidth / (config.sp_width / 8)))
assert(smemSize == config.sp_capacity.asInstanceOf[CapacityInKilobytes].kilobytes * 1024) assert(smemSize == config.sp_capacity.asInstanceOf[CapacityInKilobytes].kilobytes * 1024)
} }