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Remove redundant coal edge handling code

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This commit is contained in:
Hansung Kim
2023-03-27 14:37:08 -07:00
parent d951de7810
commit 434013f816
1 changed files with 10 additions and 21 deletions
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31
src/main/scala/tilelink/Coalescing.scala
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@@ -94,12 +94,16 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
// queues between input and output edges to buffer requests and responses. // queues between input and output edges to buffer requests and responses.
// See IdentityNode definition in `diplomacy/Nodes.scala`. // See IdentityNode definition in `diplomacy/Nodes.scala`.
(outer.node.in zip outer.node.out).zipWithIndex.foreach { (outer.node.in zip outer.node.out).zipWithIndex.foreach {
case (((_, edgeIn), _), 0) => case (((tlIn, edgeIn), (tlOut, _)), 0) =>
// No need to do anything on the edge from coalescerNode
assert( assert(
edgeIn.master.masters(0).name == "CoalescerNode", edgeIn.master.masters(0).name == "CoalescerNode",
"First edge is not connected to the coalescer master node" "First edge is not connected to the coalescer master node"
) )
// Edge from the coalescer TL master node should simply bypass the identity node,
// except for connecting the outgoing edge to the inflight table, which is done
// down below.
tlOut.a <> tlIn.a
tlIn.d <> tlOut.d
case (((tlIn, edgeIn), (tlOut, edgeOut)), i) => case (((tlIn, edgeIn), (tlOut, edgeOut)), i) =>
// Request queue // Request queue
// //
@@ -176,7 +180,6 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
} }
// Generate coalesced requests // Generate coalesced requests
// FIXME: currently generating bogus coalesced requests
val coalSourceId = RegInit(0.U(2.W /* FIXME hardcoded */ )) val coalSourceId = RegInit(0.U(2.W /* FIXME hardcoded */ ))
coalSourceId := coalSourceId + 1.U coalSourceId := coalSourceId + 1.U
@@ -243,10 +246,11 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
def getCoalescedDataChunk(data: UInt, dataWidth: Int, offset: UInt, size: Int): UInt = { def getCoalescedDataChunk(data: UInt, dataWidth: Int, offset: UInt, size: Int): UInt = {
val sizeMask = (1.U << size) - 1.U val sizeMask = (1.U << size) - 1.U
assert(dataWidth % size == 0, "coalesced data width not evenly divisible by size") assert(dataWidth % size == 0, "coalesced data width not evenly divisible by size")
val chunks = Wire(Vec(dataWidth / size, UInt(size.W))) val numChunks = dataWidth / size
val offsets = (0 until dataWidth / size) val chunks = Wire(Vec(numChunks, UInt(size.W)))
val offsets = (0 until numChunks)
(chunks zip offsets).foreach { case (c, o) => (chunks zip offsets).foreach { case (c, o) =>
// Take [(off-1)*size:off*size] // Take [(off-1)*size:off*size] starting from MSB
c := (data >> (dataWidth - (o + 1) * size)) & sizeMask c := (data >> (dataWidth - (o + 1) * size)) & sizeMask
} }
chunks(offset) chunks(offset)
@@ -284,21 +288,6 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
} }
} }
(outer.node.in zip outer.node.out)(0) match {
case ((tlIn, edgeIn), (tlOut, _)) =>
assert(
edgeIn.master.masters.length == 1 &&
edgeIn.master.masters(0).name == "CoalescerNode",
"First edge is not connected to the coalescer master node"
)
// TODO: do we need to do anything here?
tlOut.a <> tlIn.a
tlIn.d <> tlOut.d
dontTouch(tlIn.d)
dontTouch(tlOut.d)
}
// Debug // Debug
dontTouch(coalReqValid) dontTouch(coalReqValid)
dontTouch(coalReqAddress) dontTouch(coalReqAddress)