diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
new file mode 100644
index 0000000..dccc7c2
--- /dev/null
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -0,0 +1,14 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.tilelink
+
+import chisel3._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.unittest._
+
+class CoalescingUnitTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
+  dut.io.start := io.start
+  io.finished := true.B
+}