support no gemminis, trim debug prints

This commit is contained in:
Richard Yan
2024-11-11 16:14:02 -08:00
parent 465322af38
commit 6488cb5c78
5 changed files with 15 additions and 9 deletions

View File

@@ -44,7 +44,7 @@ class AlignFilterNode(filters: Seq[AddressSet])(implicit p: Parameters) extends
val addresses = seq.flatMap(_.slaves.flatMap(_.address))
val unifiedAddressRange = addresses.flatMap(_.toRanges).sorted.reduce(_.union(_).get)
assert(isPow2(unifiedAddressRange.size))
println(s"$name address range ${unifiedAddressRange}")
// println(s"$name address range ${unifiedAddressRange}")
seq.head.v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,

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@@ -13,7 +13,7 @@ import org.chipsalliance.diplomacy.lazymodule._
class DistributorNode(from: Int, to: Int)(implicit p: Parameters) extends LazyModule {
require(isPow2(from) && isPow2(to) && (from >= to), "invalid distributor node parameters")
println(s"distributor node to segment from $from into $to")
// println(s"distributor node to segment from $from into $to")
val numClients = from / to
val node = TLNexusNode(clientFn = seq => {
@@ -54,13 +54,13 @@ class DistributorNode(from: Int, to: Int)(implicit p: Parameters) extends LazyMo
lazy val module = new LazyModuleImp(this) {
val cn = node.in.head._1
val mn = node.out.map(_._1)
println(f"$name node in size ${node.in.size}, out size ${node.out.size}")
// println(f"$name node in size ${node.in.size}, out size ${node.out.size}")
assert(node.out.size == numClients, s"got ${node.out.size} clients instead of $numClients")
// A channel
val ca = cn.a.bits
mn.map(_.a.bits).zipWithIndex.foreach { case (m, i) =>
println(s"$i master source id width ${m.source.getWidth}, client source id width ${ca.source.getWidth}")
// println(s"$i master source id width ${m.source.getWidth}, client source id width ${ca.source.getWidth}")
m.opcode := ca.opcode
m.param := ca.param
m.user := ca.user

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@@ -26,7 +26,7 @@ class RWSplitterNode(visibility: Option[AddressSet], override val name: String =
val visibilities = seq.flatMap(_.masters.flatMap(_.visibility))
val unified_vis = if (visibilities.map(_ == AddressSet.everything).reduce(_ || _)) Seq(AddressSet.everything)
else AddressSet.unify(visibilities)
println(s"$name has input visibilities $visibilities, unified to $unified_vis")
// println(s"$name has input visibilities $visibilities, unified to $unified_vis")
seq.head.v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),

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@@ -98,8 +98,10 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp(
g.cmd.valid := VecInit(active).reduceTree(_ || _)
}
if (gemminiAccs.nonEmpty) {
// this might need some more tweaking (e.g. bitmask instead of or)
coreAccs.foreach(_.status := VecInit(gemminiAccs.map(_.status)).reduceTree(_ | _))
}
(outer.traceTLNode.in.map(_._1) zip outer.traceTLNode.out.map(_._1)).foreach { case (i, o) =>
o.a <> i.a

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@@ -96,9 +96,13 @@ class VirgoSharedMemComponents(
}
Seq.fill(smemWidth / spWidthBytes)(fanout).flatten // smem wider than spad, duplicate masters
}
if (nodes.isEmpty) {
Seq.fill(smemSubbanks)(Seq())
} else {
// (gemmini, word) => (word, gemmini)
wordFanoutNodes.transpose
}
}
// (banks, subbanks, gemminis)
val spadReadNodes = Seq.fill(smemBanks)(distAndDuplicate(gemminis.map(_.spad_read_nodes), "r"))