From 71edc439a0c131491f244965f8d8948899d84e15 Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Wed, 8 May 2024 11:41:33 -0700 Subject: [PATCH] revert lsuq size --- src/main/scala/radiance/tile/RadianceTile.scala | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala index 534da44..cf06ed9 100644 --- a/src/main/scala/radiance/tile/RadianceTile.scala +++ b/src/main/scala/radiance/tile/RadianceTile.scala @@ -194,11 +194,8 @@ class RadianceTile private ( val imemTagWidth = UUID_WIDTH + NW_WIDTH require(numWarps >= numLsuLanes, - s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})") - val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes) - require(LSUQ_SIZE == p(SIMTCoreKey).get.nSrcIds, - s"LSUQ_SIZE (${LSUQ_SIZE}) != nSrcIds (${p(SIMTCoreKey).get.nSrcIds})" - + " which can result in TileLink srcId underutilization") + s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})") + val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds val LSUQ_TAG_BITS = log2Ceil(LSUQ_SIZE) + 1 /*DCACHE_BATCH_SEL_BITS*/ val dmemTagWidth = UUID_WIDTH + LSUQ_TAG_BITS // dmem and smem shares the same tag width, DCACHE_NOSM_TAG_WIDTH