diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala
index 215d9f8..a23763c 100644
--- a/src/main/scala/radiance/tile/RadianceTile.scala
+++ b/src/main/scala/radiance/tile/RadianceTile.scala
@@ -287,7 +287,8 @@ class RadianceTile private (
         supports = TLSlaveToMasterTransferSizes(
           probe = TransferSizes(1, tcSmemSize),
           get = TransferSizes(1, tcSmemSize),
-        )
+        ),
+        requestFifo = true
       ))
     )))
   }
diff --git a/src/main/scala/radiance/tile/VirgoSharedMemComponents.scala b/src/main/scala/radiance/tile/VirgoSharedMemComponents.scala
index 5e666cf..5de9481 100644
--- a/src/main/scala/radiance/tile/VirgoSharedMemComponents.scala
+++ b/src/main/scala/radiance/tile/VirgoSharedMemComponents.scala
@@ -60,6 +60,7 @@ class VirgoSharedMemComponents(
   }
   val tcNodeFanouts = radianceTiles.flatMap(_.tcSmemNodes)
     // .map(connectOne(_, () => TLBuffer(BufferParams(2, false, false), BufferParams(0))))
+    .map(connectOne(_, () => TLFIFOFixer()))
     .map(connectXbarName(_, Some("tc_fanout")))
   val clBusClients: Seq[TLNode] = radianceSmemFanout