From 765c8ef1b095df6c72ba8f2c8b93b7940f15ffb7 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 17 Nov 2023 19:12:35 -0800 Subject: [PATCH] Remove unnecessary write ack filtering logic in VortexTLAdapter --- src/main/scala/tile/VortexTile.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tile/VortexTile.scala b/src/main/scala/tile/VortexTile.scala index 27ce62a..d4c56de 100644 --- a/src/main/scala/tile/VortexTile.scala +++ b/src/main/scala/tile/VortexTile.scala @@ -593,8 +593,8 @@ class VortexTLAdapter( io.outReq.bits.corrupt := 0.U io.inReq.ready := io.outReq.ready // VortexBundleD <> TLBundleD - // Do not reply to write requests; Vortex core does not expect ack on writes - io.inResp.valid := io.outResp.valid && edge.hasData(io.outResp.bits) + // Filtering out write requests is handled inside the wrapper Verilog + io.inResp.valid := io.outResp.valid io.inResp.bits.opcode := io.outResp.bits.opcode io.inResp.bits.size := io.outResp.bits.size io.inResp.bits.source := io.outResp.bits.source