Add EmulatorTile
also split core-specific config keys from radiance.memory to radiance.core.
This commit is contained in:
Hansung Kim
31
src/main/resources/csrc/SimEmulator.cc
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31
src/main/resources/csrc/SimEmulator.cc
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@@ -0,0 +1,31 @@
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#ifndef NO_VPI
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#include <vpi_user.h>
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#include <svdpi.h>
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#endif
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#include <stdint.h>
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extern "C" void emulator_init_rs(int num_lanes);
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extern "C" void emulator_generate_rs(uint8_t *vec_a_ready, uint8_t *vec_a_valid,
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long long *vec_a_address,
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uint8_t *vec_a_is_store, int *vec_a_size,
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long long *vec_a_data, uint8_t *vec_d_ready,
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uint8_t *vec_d_valid,
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uint8_t *vec_d_is_store, int *vec_d_size,
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uint8_t inflight, uint8_t *finished);
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extern "C" void emulator_init(int num_lanes) {
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emulator_init_rs(num_lanes);
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}
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extern "C" void emulator_generate(uint8_t *vec_a_ready, uint8_t *vec_a_valid,
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long long *vec_a_address,
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uint8_t *vec_a_is_store, int *vec_a_size,
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long long *vec_a_data, uint8_t *vec_d_ready,
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uint8_t *vec_d_valid, uint8_t *vec_d_is_store,
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int *vec_d_size, uint8_t inflight,
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uint8_t *finished) {
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emulator_generate_rs(vec_a_ready, vec_a_valid, vec_a_address, vec_a_is_store,
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vec_a_size, vec_a_data, vec_d_ready, vec_d_valid,
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vec_d_is_store, vec_d_size, inflight, finished);
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}
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132
src/main/resources/vsrc/SimEmulator.v
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132
src/main/resources/vsrc/SimEmulator.v
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@@ -0,0 +1,132 @@
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`include "SimDefaults.vh"
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import "DPI-C" function void emulator_init(
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input longint num_lanes
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);
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// Make sure to sync the parameters for:
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// (1) import "DPI-C" declaration
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// (2) C function declaration
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// (3) DPI function calls inside initial/always blocks
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import "DPI-C" function void emulator_generate
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(
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input bit vec_a_ready[`MAX_NUM_LANES],
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output bit vec_a_valid[`MAX_NUM_LANES],
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output longint vec_a_address[`MAX_NUM_LANES],
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output bit vec_a_is_store[`MAX_NUM_LANES],
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output int vec_a_size[`MAX_NUM_LANES],
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output longint vec_a_data[`MAX_NUM_LANES],
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output bit vec_d_ready[`MAX_NUM_LANES],
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input bit vec_d_valid[`MAX_NUM_LANES],
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input bit vec_d_is_store[`MAX_NUM_LANES],
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input int vec_d_size[`MAX_NUM_LANES],
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input bit inflight,
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output bit finished
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);
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module SimEmulator #(parameter NUM_LANES = 4) (
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input clock,
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input reset,
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input [NUM_LANES-1:0] a_ready,
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output [NUM_LANES-1:0] a_valid,
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output [`SIMMEM_DATA_WIDTH*NUM_LANES-1:0] a_address,
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output [NUM_LANES-1:0] a_is_store,
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output [`SIMMEM_LOGSIZE_WIDTH*NUM_LANES-1:0] a_size,
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output [`SIMMEM_DATA_WIDTH*NUM_LANES-1:0] a_data,
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output [NUM_LANES-1:0] d_ready,
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input [NUM_LANES-1:0] d_valid,
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input [NUM_LANES-1:0] d_is_store,
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input [`SIMMEM_LOGSIZE_WIDTH*NUM_LANES-1:0] d_size,
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// TODO: d_mask
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// TODO: d_data
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input inflight,
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output finished
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);
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// "in": C->verilog, "out": verilog->C
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// need to be in ascending order to match with C indexing
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// C array sizes are static, so need to use MAX_NUM_LANES
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bit __out_a_ready [0:`MAX_NUM_LANES-1];
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bit __in_a_valid [0:`MAX_NUM_LANES-1];
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longint __in_a_address [0:`MAX_NUM_LANES-1];
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bit __in_a_is_store [0:`MAX_NUM_LANES-1];
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int __in_a_size [0:`MAX_NUM_LANES-1];
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longint __in_a_data [0:`MAX_NUM_LANES-1];
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bit __in_d_ready [0:`MAX_NUM_LANES-1];
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bit __out_d_valid [0:`MAX_NUM_LANES-1];
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bit __out_d_is_store [0:`MAX_NUM_LANES-1];
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int __out_d_size [0:`MAX_NUM_LANES-1];
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bit __out_inflight;
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bit __in_finished;
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genvar g;
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generate
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for (g = 0; g < NUM_LANES; g = g + 1) begin
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assign __out_a_ready[g] = a_ready[g];
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assign a_valid[g] = __in_a_valid[g];
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assign a_address[`SIMMEM_DATA_WIDTH*g +: `SIMMEM_DATA_WIDTH]
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= __in_a_address[g][`SIMMEM_DATA_WIDTH-1:0];
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assign a_is_store[g] = __in_a_is_store[g];
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assign a_size[`SIMMEM_LOGSIZE_WIDTH*g +: `SIMMEM_LOGSIZE_WIDTH]
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= __in_a_size[g][`SIMMEM_LOGSIZE_WIDTH-1:0];
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assign a_data[`SIMMEM_DATA_WIDTH*g +: `SIMMEM_DATA_WIDTH]
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= __in_a_data[g][`SIMMEM_DATA_WIDTH-1:0];
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assign d_ready[g] = __in_d_ready[g];
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assign __out_d_valid[g] = d_valid[g];
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assign __out_d_is_store[g] = d_is_store[g];
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assign __out_d_size[g] = d_size[`SIMMEM_LOGSIZE_WIDTH*g +: `SIMMEM_LOGSIZE_WIDTH];
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end
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assign __out_inflight = inflight;
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endgenerate
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assign finished = __in_finished;
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initial begin
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emulator_init(NUM_LANES);
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end
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// negedge is important here; the DPI logic is essentially functioning as
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// a combinational logic, so we want to reflect the signal change from DPI
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// at the *current* cycle, not the next.
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always @(negedge clock) begin
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if (reset) begin
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for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
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__in_a_valid[tid] = 1'b0;
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__in_a_address[tid] = `SIMMEM_DATA_WIDTH'b0;
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__in_a_is_store[tid] = 1'b0;
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__in_a_size[tid] = 32'b0;
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__in_a_data[tid] = `SIMMEM_DATA_WIDTH'b0;
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__in_d_ready[tid] = 1'b0;
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end
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__in_finished = 1'b0;
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end else begin
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emulator_generate(
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__out_a_ready,
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__in_a_valid,
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__in_a_address,
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__in_a_is_store,
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__in_a_size,
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__in_a_data,
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__in_d_ready,
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__out_d_valid,
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__out_d_is_store,
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__out_d_size,
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__out_inflight,
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__in_finished
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);
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for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
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$display("verilog: %04d a_valid[%d]=%d, a_address[%d]=0x%x, d_ready[%d]=%d",
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$time, tid, __in_a_valid[tid], tid, __in_a_address[tid], tid, __in_d_ready[tid]);
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end
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if (finished) begin
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$finish;
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end
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end
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end
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endmodule
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243
src/main/scala/radiance/core/Emulator.scala
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243
src/main/scala/radiance/core/Emulator.scala
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@@ -0,0 +1,243 @@
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package radiance.core
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config.{Field, Parameters}
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import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.diplomacy.{IdRange, AddressSet, BufferParams}
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import radiance.memory.{SourceGenerator, TraceLine, TLPrintf}
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case class SIMTCoreParams(
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nWarps: Int = 4, // # of warps in the core
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nCoreLanes: Int = 4, // # of SIMT threads in the core
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nMemLanes: Int = 4, // # of memory lanes in the memory interface to the
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// cache; relates to the LSU lanes
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nSrcIds: Int = 8 // # of source IDs allocated to each of the nMemLanes
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)
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case class MemtraceCoreParams(
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tracefilename: String = "undefined",
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traceHasSource: Boolean = false
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)
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case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None /*default*/ )
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case object MemtraceCoreKey
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extends Field[Option[MemtraceCoreParams]](None /*default*/ )
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// #############################################################################
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// FIXME: copy-paste from MemFuzzer
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// #############################################################################
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class Emulator(
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numLanes: Int,
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numSrcIds: Int,
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wordSizeInBytes: Int,
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)(implicit p: Parameters)
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extends LazyModule {
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val laneNodes = Seq.tabulate(numLanes) { i =>
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val clientParam = Seq(
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TLMasterParameters.v1(
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name = "Emulator" + i.toString,
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sourceId = IdRange(0, numSrcIds)
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// visibility = Seq(AddressSet(0x0000, 0xffffff))
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)
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)
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TLClientNode(Seq(TLMasterPortParameters.v1(clientParam)))
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}
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val node = TLIdentityNode()
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laneNodes.foreach(node := _)
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lazy val module = new EmulatorImp(this, numLanes, numSrcIds, wordSizeInBytes)
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}
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class EmulatorImp(
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outer: Emulator,
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numLanes : Int,
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numSrcIds: Int,
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wordSizeInBytes: Int,
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) extends LazyModuleImp(outer) {
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val io = IO(new Bundle {
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val finished = Output(Bool())
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})
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val sim = Module(new SimEmulator(numLanes))
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sim.io.clock := clock
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sim.io.reset := reset.asBool
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sim.io.a.ready := VecInit(outer.laneNodes.map { node =>
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val (tlOut, _) = node.out(0)
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tlOut.a.ready
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}).asUInt
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io.finished := sim.io.finished
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// connect Verilog <-> Chisel IO
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// Verilog IO flattened across all lanes
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val laneReqs = Wire(Vec(numLanes, Decoupled(new TraceLine)))
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val addrW = laneReqs(0).bits.address.getWidth
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val sizeW = laneReqs(0).bits.size.getWidth
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val dataW = laneReqs(0).bits.data.getWidth
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laneReqs.zipWithIndex.foreach { case (req, i) =>
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req.valid := sim.io.a.valid(i)
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req.bits.source := 0.U // DPI doesn't generate contain source id
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req.bits.address := sim.io.a.address(addrW * (i + 1) - 1, addrW * i)
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req.bits.is_store := sim.io.a.is_store(i)
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req.bits.size := sim.io.a.size(sizeW * (i + 1) - 1, sizeW * i)
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req.bits.data := sim.io.a.data(dataW * (i + 1) - 1, dataW * i)
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}
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sim.io.a.ready := VecInit(laneReqs.map(_.ready)).asUInt
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val laneResps = Wire(Vec(numLanes, Flipped(Decoupled(new TraceLine))))
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laneResps.zipWithIndex.foreach { case (resp, i) =>
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resp.ready := sim.io.d.ready(i)
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// TODO: not handled in DPI
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resp.bits.source := DontCare
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resp.bits.address := DontCare
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resp.bits.data := DontCare
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}
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sim.io.d.valid := VecInit(laneResps.map(_.valid)).asUInt
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sim.io.d.is_store := VecInit(laneResps.map(_.bits.is_store)).asUInt
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sim.io.d.size := VecInit(laneResps.map(_.bits.size)).asUInt
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val sourceGens = Seq.fill(numLanes)(
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Module(
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new SourceGenerator(
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log2Ceil(numSrcIds),
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ignoreInUse = false
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)
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)
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)
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val anyInflight = sourceGens.map(_.io.inflight).reduce(_ || _)
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sim.io.inflight := anyInflight
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// Take requests off of the queue and generate TL requests
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(outer.laneNodes zip (laneReqs zip laneResps)).zipWithIndex.foreach {
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case ((node, (req, resp)), lane) =>
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val (tlOut, edge) = node.out(0)
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// Requests --------------------------------------------------------------
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//
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// Core only makes accesses of granularity larger than a word, so we want
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// the trace driver to act so as well.
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// That means if req.size is smaller than word size, we need to pad data
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// with zeros to generate a word-size request, and set mask accordingly.
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val offsetInWord = req.bits.address % wordSizeInBytes.U
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val subword = req.bits.size < log2Ceil(wordSizeInBytes).U
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// `mask` is currently unused
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// val mask = Wire(UInt(wordSizeInBytes.W))
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val wordData = Wire(UInt((wordSizeInBytes * 8 * 2).W))
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val sizeInBytes = Wire(UInt((sizeW + 1).W))
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sizeInBytes := (1.U) << req.bits.size
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// mask := Mux(subword, (~((~0.U(64.W)) << sizeInBytes)) << offsetInWord, ~0.U)
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wordData := Mux(subword, req.bits.data << (offsetInWord * 8.U), req.bits.data)
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val wordAlignedAddress =
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req.bits.address & ~((1 << log2Ceil(wordSizeInBytes)) - 1).U(addrW.W)
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val wordAlignedSize = Mux(subword, 2.U, req.bits.size)
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val sourceGen = sourceGens(lane)
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sourceGen.io.gen := tlOut.a.fire
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sourceGen.io.reclaim.valid := tlOut.d.fire
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sourceGen.io.reclaim.bits := tlOut.d.bits.source
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sourceGen.io.meta := DontCare
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val (plegal, pbits) = edge.Put(
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fromSource = sourceGen.io.id.bits,
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toAddress = wordAlignedAddress,
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lgSize = wordAlignedSize, // trace line already holds log2(size)
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// data should be aligned to beatBytes
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data =
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(wordData << (8.U * (wordAlignedAddress % edge.manager.beatBytes.U))).asUInt
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)
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val (glegal, gbits) = edge.Get(
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fromSource = sourceGen.io.id.bits,
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toAddress = wordAlignedAddress,
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lgSize = wordAlignedSize
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)
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val legal = Mux(req.bits.is_store, plegal, glegal)
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val bits = Mux(req.bits.is_store, pbits, gbits)
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tlOut.a.valid := req.valid && sourceGen.io.id.valid
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req.ready := tlOut.a.ready && sourceGen.io.id.valid
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when(tlOut.a.fire) {
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assert(legal, "illegal TL req gen")
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}
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tlOut.a.bits := bits
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// Responses -------------------------------------------------------------
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//
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tlOut.d.ready := resp.ready
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resp.valid := tlOut.d.valid
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resp.bits.is_store := !edge.hasData(tlOut.d.bits)
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resp.bits.size := tlOut.d.bits.size
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tlOut.b.ready := true.B
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tlOut.c.valid := false.B
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tlOut.e.valid := false.B
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// debug
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dontTouch(req)
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when(tlOut.a.valid) {
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printf(s"Lane ${lane}: ");
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TLPrintf(
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"Emulator",
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tlOut.a.bits.source,
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tlOut.a.bits.address,
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tlOut.a.bits.size,
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tlOut.a.bits.mask,
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req.bits.is_store,
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tlOut.a.bits.data,
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req.bits.data
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)
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}
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dontTouch(tlOut.a)
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dontTouch(tlOut.d)
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}
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// when(traceFinished && allReqReclaimed && noValidReqs) {
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// assert(
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// false.B,
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// "\n\n\nsimulation Successfully finished\n\n\n (this assertion intentional fail upon MemTracer termination)"
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// )
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// }
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}
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class SimEmulator(numLanes: Int)
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extends BlackBox(Map("NUM_LANES" -> numLanes))
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with HasBlackBoxResource {
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val traceLineT = new TraceLine
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val addrW = traceLineT.address.getWidth
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val sizeW = traceLineT.size.getWidth
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val dataW = traceLineT.data.getWidth
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val io = IO(new Bundle {
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val clock = Input(Clock())
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val reset = Input(Bool())
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val inflight = Input(Bool())
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val finished = Output(Bool())
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val a =
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new Bundle {
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val ready = Input(UInt(numLanes.W))
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val valid = Output(UInt(numLanes.W))
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// Chisel can't interface with Verilog 2D port, so flatten all lanes into
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// single wide 1D array.
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val address = Output(UInt((addrW * numLanes).W))
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val is_store = Output(UInt(numLanes.W))
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val size = Output(UInt((sizeW * numLanes).W))
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val data = Output(UInt((dataW * numLanes).W))
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}
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val d =
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new Bundle {
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val ready = Output(UInt(numLanes.W))
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val valid = Input(UInt(numLanes.W))
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val is_store = Input(UInt(numLanes.W))
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val size = Input(UInt((sizeW * numLanes).W))
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}
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})
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addResource("/vsrc/SimDefaults.vh")
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addResource("/vsrc/SimEmulator.v")
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addResource("/csrc/SimEmulator.cc")
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}
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@@ -4,6 +4,7 @@ import freechips.rocketchip.diplomacy.LazyModule
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import freechips.rocketchip.subsystem._
|
||||
import org.chipsalliance.cde.config.Parameters
|
||||
import freechips.rocketchip.tilelink._
|
||||
import radiance.core.{SIMTCoreKey, MemtraceCoreKey}
|
||||
|
||||
// TODO: possibly move to somewhere closer to CoalescingUnit
|
||||
// TODO: separate coalescer config from CanHaveMemtraceCore
|
||||
|
||||
@@ -10,25 +10,10 @@ import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
|
||||
import freechips.rocketchip.util.{Code, MultiPortQueue, OnePortLanePositionedQueue}
|
||||
import freechips.rocketchip.unittest._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import radiance.core.{SIMTCoreParams, SIMTCoreKey}
|
||||
|
||||
// TODO: find better place for these
|
||||
|
||||
case class SIMTCoreParams(
|
||||
nWarps: Int = 4, // # of warps in the core
|
||||
nCoreLanes: Int = 4, // # of SIMT threads in the core
|
||||
nMemLanes: Int = 4, // # of memory lanes in the memory interface to the
|
||||
// cache; relates to the LSU lanes
|
||||
nSrcIds: Int = 8 // # of source IDs allocated to each of the nMemLanes
|
||||
)
|
||||
case class MemtraceCoreParams(
|
||||
tracefilename: String = "undefined",
|
||||
traceHasSource: Boolean = false
|
||||
)
|
||||
case class CoalXbarParam()
|
||||
|
||||
case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None /*default*/ )
|
||||
case object MemtraceCoreKey
|
||||
extends Field[Option[MemtraceCoreParams]](None /*default*/ )
|
||||
case object CoalescerKey
|
||||
extends Field[Option[CoalescerConfig]](None /*default*/ )
|
||||
case object CoalXbarKey extends Field[Option[CoalXbarParam]](None /*default*/ )
|
||||
|
||||
@@ -12,6 +12,7 @@ import freechips.rocketchip.subsystem._
|
||||
import gemmini._
|
||||
import gemmini.Arithmetic.FloatArithmetic._
|
||||
import radiance.tile._
|
||||
import radiance.core._
|
||||
import radiance.memory._
|
||||
import radiance.subsystem.RadianceGemminiDataType.{BF16, FP16, FP32, Int8}
|
||||
|
||||
@@ -106,6 +107,44 @@ class WithRadianceCores(
|
||||
), tensorCoreFP16, tensorCoreDecoupled, useVxCache)
|
||||
}
|
||||
|
||||
class WithEmulatorCores(
|
||||
n: Int,
|
||||
useVxCache: Boolean
|
||||
) extends Config((site, _, up) => {
|
||||
case TilesLocated(InSubsystem) => {
|
||||
val prev = up(TilesLocated(InSubsystem))
|
||||
val idOffset = up(NumTiles)
|
||||
val emulator = EmulatorTileParams(
|
||||
core = VortexCoreParams(),
|
||||
useVxCache = useVxCache)
|
||||
List.tabulate(n)(i => EmulatorTileAttachParams(
|
||||
emulator.copy(tileId = i + idOffset),
|
||||
RocketCrossingParams()
|
||||
)) ++ prev
|
||||
}
|
||||
case NumTiles => up(NumTiles) + 1
|
||||
case NumRadianceCores => up(NumRadianceCores) + 1
|
||||
})
|
||||
|
||||
class WithFuzzerCores(
|
||||
n: Int,
|
||||
useVxCache: Boolean
|
||||
) extends Config((site, _, up) => {
|
||||
case TilesLocated(InSubsystem) => {
|
||||
val prev = up(TilesLocated(InSubsystem))
|
||||
val idOffset = up(NumTiles)
|
||||
val fuzzer = FuzzerTileParams(
|
||||
core = VortexCoreParams(),
|
||||
useVxCache = useVxCache)
|
||||
List.tabulate(n)(i => FuzzerTileAttachParams(
|
||||
fuzzer.copy(tileId = i + idOffset),
|
||||
RocketCrossingParams()
|
||||
)) ++ prev
|
||||
}
|
||||
case NumTiles => up(NumTiles) + 1
|
||||
case NumRadianceCores => up(NumRadianceCores) + 1
|
||||
})
|
||||
|
||||
object RadianceGemminiDataType extends Enumeration {
|
||||
type Type = Value
|
||||
val FP32, FP16, BF16, Int8 = Value
|
||||
@@ -244,25 +283,6 @@ class WithRadianceFrameBuffer(baseAddress: BigInt,
|
||||
}
|
||||
})
|
||||
|
||||
class WithFuzzerCores(
|
||||
n: Int,
|
||||
useVxCache: Boolean
|
||||
) extends Config((site, _, up) => {
|
||||
case TilesLocated(InSubsystem) => {
|
||||
val prev = up(TilesLocated(InSubsystem))
|
||||
val idOffset = up(NumTiles)
|
||||
val fuzzer = FuzzerTileParams(
|
||||
core = VortexCoreParams(),
|
||||
useVxCache = useVxCache)
|
||||
List.tabulate(n)(i => FuzzerTileAttachParams(
|
||||
fuzzer.copy(tileId = i + idOffset),
|
||||
RocketCrossingParams()
|
||||
)) ++ prev
|
||||
}
|
||||
case NumTiles => up(NumTiles) + 1
|
||||
case NumRadianceCores => up(NumRadianceCores) + 1
|
||||
})
|
||||
|
||||
class WithRadianceCluster(
|
||||
clusterId: Int,
|
||||
location: HierarchicalLocation = InSubsystem,
|
||||
|
||||
96
src/main/scala/radiance/tile/EmulatorTile.scala
Normal file
96
src/main/scala/radiance/tile/EmulatorTile.scala
Normal file
@@ -0,0 +1,96 @@
|
||||
// See LICENSE.SiFive for license details.
|
||||
// See LICENSE.Berkeley for license details.
|
||||
|
||||
package radiance.tile
|
||||
|
||||
import chisel3._
|
||||
import org.chipsalliance.cde.config.Parameters
|
||||
import org.chipsalliance.diplomacy.lazymodule.LazyModule
|
||||
import freechips.rocketchip.resources.SimpleDevice
|
||||
import freechips.rocketchip.prci.ClockCrossingType
|
||||
import freechips.rocketchip.rocket._
|
||||
import freechips.rocketchip.tile._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.subsystem.{HierarchicalElementCrossingParamsLike, CanAttachTile}
|
||||
import freechips.rocketchip.prci.{ClockSinkParameters}
|
||||
import radiance.core._
|
||||
import radiance.memory.{CoalescingUnit, CoalescerKey}
|
||||
|
||||
// TODO: De-duplicate between this and FuzzerTile
|
||||
|
||||
case class EmulatorTileParams(
|
||||
core: VortexCoreParams = VortexCoreParams(), // TODO: remove this
|
||||
useVxCache: Boolean = false,
|
||||
tileId: Int = 0,
|
||||
) extends InstantiableTileParams[EmulatorTile] {
|
||||
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(
|
||||
implicit p: Parameters
|
||||
): EmulatorTile = {
|
||||
new EmulatorTile(this, crossing, lookup)
|
||||
}
|
||||
val clockSinkParams = ClockSinkParameters()
|
||||
val blockerCtrlAddr = None
|
||||
val icache = None
|
||||
val dcache = None
|
||||
val btb = None
|
||||
val baseName = "radiance_emulator_tile"
|
||||
val uniqueName = s"${baseName}_$tileId"
|
||||
}
|
||||
|
||||
case class EmulatorTileAttachParams(
|
||||
tileParams: EmulatorTileParams,
|
||||
crossingParams: HierarchicalElementCrossingParamsLike
|
||||
) extends CanAttachTile { type TileType = EmulatorTile }
|
||||
|
||||
class EmulatorTile private (
|
||||
val EmulatorParams: EmulatorTileParams,
|
||||
crossing: ClockCrossingType,
|
||||
lookup: LookupByHartIdImpl,
|
||||
q: Parameters
|
||||
) extends BaseTile(EmulatorParams, crossing, lookup, q)
|
||||
with SinksExternalInterrupts
|
||||
with SourcesExternalNotifications {
|
||||
def this(
|
||||
params: EmulatorTileParams,
|
||||
crossing: HierarchicalElementCrossingParamsLike,
|
||||
lookup: LookupByHartIdImpl
|
||||
)(implicit p: Parameters) =
|
||||
this(params, crossing.crossingType, lookup, p)
|
||||
|
||||
val cpuDevice: SimpleDevice = new SimpleDevice("emulator", Nil)
|
||||
|
||||
val intOutwardNode = None
|
||||
val slaveNode: TLInwardNode = TLIdentityNode()
|
||||
val masterNode = visibilityNode
|
||||
// val statusNode = BundleBridgeSource(() => new GroundTestStatus)
|
||||
|
||||
val (numLanes, numSrcIds) = p(SIMTCoreKey) match {
|
||||
case Some(param) => (param.nMemLanes, param.nSrcIds)
|
||||
case None => {
|
||||
require(false, "emulator requires SIMTCoreKey to be defined")
|
||||
(0, 0)
|
||||
}
|
||||
}
|
||||
// FIXME: parameterize
|
||||
val wordSizeInBytes = 4
|
||||
|
||||
val emulator = LazyModule(new Emulator(numLanes, numSrcIds, wordSizeInBytes))
|
||||
|
||||
// Conditionally instantiate memory coalescer
|
||||
val coalescerNode = p(CoalescerKey) match {
|
||||
case Some(coalParam) => {
|
||||
val coal = LazyModule(new CoalescingUnit(coalParam))
|
||||
coal.cpuNode :=* TLWidthWidget(4) :=* emulator.node
|
||||
coal.aggregateNode
|
||||
}
|
||||
case None => emulator.node
|
||||
}
|
||||
|
||||
masterNode :=* coalescerNode
|
||||
|
||||
override lazy val module = new EmulatorTileModuleImp(this)
|
||||
}
|
||||
|
||||
class EmulatorTileModuleImp(outer: EmulatorTile) extends BaseTileModuleImp(outer) {
|
||||
outer.reportCease(Some(outer.emulator.module.io.finished))
|
||||
}
|
||||
@@ -13,6 +13,7 @@ import freechips.rocketchip.tile._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.subsystem.{HierarchicalElementCrossingParamsLike, CanAttachTile}
|
||||
import freechips.rocketchip.prci.{ClockSinkParameters}
|
||||
import radiance.core.{SIMTCoreKey}
|
||||
import radiance.memory._
|
||||
|
||||
case class FuzzerTileParams(
|
||||
|
||||
@@ -19,6 +19,7 @@ import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
import midas.targetutils.SynthesizePrintf
|
||||
import org.chipsalliance.cde.config._
|
||||
import radiance.core._
|
||||
import radiance.memory._
|
||||
import radiance.subsystem.{GPUMemParams, GPUMemory, RadianceSimArgs}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user