diff --git a/radiance.mk b/radiance.mk index f286092..196cf22 100644 --- a/radiance.mk +++ b/radiance.mk @@ -21,6 +21,7 @@ EXTRA_SIM_PREPROC_DEFINES += \ +define+ICACHE_DISABLE +define+DCACHE_DISABLE \ +define+GBAR_ENABLE \ +define+GBAR_CLUSTER_ENABLE \ + +define+FPU_FPNEW \ +define+NUM_BARRIERS=8 \ +define+NUM_CORES=2 +define+NUM_THREADS=8 +define+NUM_WARPS=8 # Can't increase this to above 14, since the binary accesses 0xff0040.. diff --git a/src/main/scala/radiance/memory/Coalescing.scala b/src/main/scala/radiance/memory/Coalescing.scala index 13a01a5..e19467f 100644 --- a/src/main/scala/radiance/memory/Coalescing.scala +++ b/src/main/scala/radiance/memory/Coalescing.scala @@ -354,7 +354,7 @@ class SourceGenerator[T <: Data]( } when(io.reclaim.valid) { // @perf: would this require multiple write ports? - // NOTE: this does not seem sufficient to handle same-cycle gen-reclaimon + // NOTE: this does not seem sufficient to handle same-cycle gen-reclaim on // its own occupancyTable(io.reclaim.bits).valid := false.B // mark freed } diff --git a/src/main/scala/radiance/tile/GemminiTile.scala b/src/main/scala/radiance/tile/GemminiTile.scala index 2571843..ccb7515 100644 --- a/src/main/scala/radiance/tile/GemminiTile.scala +++ b/src/main/scala/radiance/tile/GemminiTile.scala @@ -140,5 +140,7 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer) tieOffGemminiRocc - outer.reportCease(None) + // hacky, but cluster will AND the cease signals from all tiles, and we want + // the core tiles to determine cluster cease not Gemmini + outer.reportCease(Some(true.B)) } diff --git a/src/main/scala/radiance/tile/VortexCore.scala b/src/main/scala/radiance/tile/VortexCore.scala index 2e6160e..b10ac58 100644 --- a/src/main/scala/radiance/tile/VortexCore.scala +++ b/src/main/scala/radiance/tile/VortexCore.scala @@ -301,7 +301,7 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters) addResource("/csrc/softfloat/include/softfloat_types.h") addResource("/csrc/softfloat/RISCV/specialize.h") - // Vortex 2.0: fp_cores/ renamed to fpu/ + // fpu addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_class.sv") addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_cvt.sv") addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_define.vh") @@ -316,23 +316,38 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters) addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_sqrt.sv") addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_to_csr_if.sv") addResource("/vsrc/vortex/hw/rtl/core/VX_fpu_unit.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fp_rounding.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/altera/stratix10/dspba_delay_ver.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/altera/stratix10/acl_fdiv.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/altera/stratix10/acl_fmadd.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/altera/arria10/dspba_delay_ver.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fp_class.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fpu_fpnew.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fp_cvt.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fp_fma.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fp_ncomp.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fpu_fpga.sv") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fpu_types.vh") - // addResource("/vsrc/vortex/hw/rtl/fp_cores/VX_fp_sqrt.sv") + + // fpnew + // compile order matters; package definitions (ex. fpnew_pkg) should be + // compiled before all the other modules that reference them. They are added + // to vcs.mk + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_cast_multi.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_classifier.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_divsqrt_multi.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_divsqrt_th_32.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_fma_multi.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_fma.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_noncomp.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_opgroup_block.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_opgroup_fmt_slice.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_opgroup_multifmt_slice.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_rounding.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_top.sv") + + addResource("/vsrc/vortex/third_party/fpnew/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv") + + // only include referenced modules in fpnew/common_cells; otherwise results + // in elaboration error + addResource("/vsrc/vortex/third_party/fpnew/src/common_cells/src/gray_to_binary.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/common_cells/src/lzc.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/common_cells/src/rr_arb_tree.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/common_cells/src/spill_register.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_branch_ctl_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_commit_csr_if.sv") @@ -346,23 +361,11 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters) addResource("/vsrc/vortex/hw/rtl/interfaces/VX_fetch_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_ibuffer_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_operands_if.sv") - // addResource("/vsrc/vortex/hw/rtl/interfaces/VX_pipeline_perf_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_sched_csr_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_schedule_if.sv") - // addResource("/vsrc/vortex/hw/rtl/interfaces/VX_sfu_csr_if.sv") - // addResource("/vsrc/vortex/hw/rtl/interfaces/VX_sfu_perf_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_warp_ctl_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_writeback_if.sv") - // addResource("/vsrc/vortex/hw/rtl/afu/vortex_afu.sv") - // addResource("/vsrc/vortex/hw/rtl/afu/ccip_std_afu.sv") - // addResource("/vsrc/vortex/hw/rtl/afu/vortex_afu.vh") - // addResource("/vsrc/vortex/hw/rtl/afu/ccip/local_mem_cfg_pkg.sv") - // addResource("/vsrc/vortex/hw/rtl/afu/ccip/ccip_if_pkg.sv") - // addResource("/vsrc/vortex/hw/rtl/afu/ccip_interface_reg.sv") - // addResource("/vsrc/vortex/hw/rtl/afu/VX_avs_wrapper.sv") - // addResource("/vsrc/vortex/hw/rtl/afu/VX_to_mem.sv") - // addResource("/vsrc/vortex/sim/vlsim/vortex_afu_shim.sv") if (tile.radianceParams.useVxCache) { addResource("/vsrc/vortex/hw/rtl/libs/VX_pending_size.sv") addResource("/vsrc/vortex/hw/rtl/cache/VX_shared_mem.sv")