wu-arch/radiance
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no tc client if not decoupled

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This commit is contained in:
Richard Yan
2024-11-11 18:16:26 -08:00
parent 6488cb5c78
commit 8c473f52e3
1 changed files with 49 additions and 42 deletions
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9
src/main/scala/radiance/tile/RadianceTile.scala
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@@ -279,7 +279,7 @@ class RadianceTile private (
}
val tcSmemSize = 32
val tcSmemNodes = Seq.tabulate(2) { i =>
val tcSmemNodes = Seq.tabulate(if (radianceParams.core.tensorCoreDecoupled) 2 else 0) { i =>
TLClientNode(Seq(TLMasterPortParameters.v2(
masters = Seq(TLMasterParameters.v2(
name = s"rad_tc_${radianceParams.coreId}_$i",
@@ -738,6 +738,7 @@ class RadianceTileModuleImp(outer: RadianceTile)
}
def connectTensor = {
if (outer.radianceParams.core.tensorCoreDecoupled) {
val tcb0 = new {
val addr = core.io.tc_a_bits_address(31, 0)
val tag = core.io.tc_a_bits_tag(outer.tensorTagWidth - 1, 0)
@@ -782,6 +783,12 @@ class RadianceTileModuleImp(outer: RadianceTile)
core.io.tc_d_bits_tag := Cat(adapters.last.io.inResp.bits.source, adapters.head.io.inResp.bits.source)
require(core.io.tc_d_bits_data.widthOption.get == adapters.head.io.inResp.bits.data.widthOption.get * 2)
require(core.io.tc_d_bits_tag.widthOption.get == adapters.head.io.inResp.bits.source.widthOption.get * 2)
} else {
core.io.tc_a_ready := false.B
core.io.tc_d_valid := false.B
core.io.tc_d_bits_data := DontCare
core.io.tc_d_bits_tag := DontCare
}
}
def connectBarrier = {