diff --git a/src/main/resources/csrc/SimMemTrace.cc b/src/main/resources/csrc/SimMemTrace.cc
index 91740ab..397773d 100644
--- a/src/main/resources/csrc/SimMemTrace.cc
+++ b/src/main/resources/csrc/SimMemTrace.cc
@@ -65,11 +65,13 @@ extern "C" void memtrace_init(const char *filename) {
 
 extern "C" void memtrace_tick(unsigned char *trace_read_valid,
                               unsigned char trace_read_ready,
-                              unsigned long *trace_read_bits) {
+                              unsigned long *trace_read_cycle,
+                              unsigned long *trace_read_address) {
   auto line = reader->tick();
 
   *trace_read_valid = line.valid;
-  *trace_read_bits = line.cycle;
+  *trace_read_cycle = line.cycle;
+  *trace_read_address = line.address;
 
   return;
 }
diff --git a/src/main/resources/vsrc/SimMemTrace.v b/src/main/resources/vsrc/SimMemTrace.v
index 18537b1..da9238d 100644
--- a/src/main/resources/vsrc/SimMemTrace.v
+++ b/src/main/resources/vsrc/SimMemTrace.v
@@ -8,7 +8,8 @@ import "DPI-C" function void memtrace_tick
 (
     output bit     trace_read_valid,
     input  bit     trace_read_ready,
-    output longint trace_read_bits
+    output longint trace_read_cycle,
+    output longint trace_read_address
 );
 
 module SimMemTrace  (
@@ -17,11 +18,13 @@ module SimMemTrace  (
 
     output                   trace_read_valid,
     input                    trace_read_ready,
-    output [`DATA_WIDTH-1:0] trace_read_bits
+    output [`DATA_WIDTH-1:0] trace_read_cycle,
+    output [`DATA_WIDTH-1:0] trace_read_address
 );
 
     bit __in_valid;
-    longint __in_bits;
+    longint __in_cycle;
+    longint __in_address;
     string __uartlog;
     int __uartno;
 
@@ -31,10 +34,12 @@ module SimMemTrace  (
     end
 
     reg __in_valid_reg;
-    reg [`DATA_WIDTH-1:0] __in_bits_reg;
+    reg [`DATA_WIDTH-1:0] __in_cycle_reg;
+    reg [`DATA_WIDTH-1:0] __in_address_reg;
 
-    assign trace_read_valid  = __in_valid_reg;
-    assign trace_read_bits   = __in_bits_reg;
+    assign trace_read_valid   = __in_valid_reg;
+    assign trace_read_cycle   = __in_cycle_reg;
+    assign trace_read_address = __in_address_reg;
 
     // Evaluate the signals on the positive edge
     always @(posedge clock) begin
@@ -42,16 +47,18 @@ module SimMemTrace  (
             __in_valid = 1'b0;
 
             __in_valid_reg <= 1'b0;
-            __in_bits_reg <= `DATA_WIDTH'b0;
+            __in_cycle_reg <= `DATA_WIDTH'b0;
         end else begin
             memtrace_tick(
                 __in_valid,
                 trace_read_ready,
-                __in_bits
+                __in_cycle,
+                __in_address
             );
 
-            __in_valid_reg  <= __in_valid;
-            __in_bits_reg   <= __in_bits;
+            __in_valid_reg   <= __in_valid;
+            __in_cycle_reg   <= __in_cycle;
+            __in_address_reg <= __in_address;
         end
     end
 
diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 082c7f5..c1edf40 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -34,7 +34,8 @@ with HasBlackBoxResource {
     val trace_read = new Bundle {
       val valid = Output(Bool())
       val ready = Input(Bool())
-      val bits = Output(UInt(64.W))
+      val cycle = Output(UInt(64.W))
+      val address = Output(UInt(64.W))
     }
   })