From 9a5af036725cf52fafe897ea96d84ab4eb32a0be Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Fri, 1 Nov 2024 02:45:08 -0700 Subject: [PATCH] blocking gemmini fence and bump vortex --- src/main/resources/vsrc/vortex | 2 +- src/main/scala/radiance/tile/GemminiTile.scala | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex index ef90261..2e3ea06 160000 --- a/src/main/resources/vsrc/vortex +++ b/src/main/resources/vsrc/vortex @@ -1 +1 @@ -Subproject commit ef902614ffb10acdb4e49d8ed963b5ab75ce93f3 +Subproject commit 2e3ea060a5d87d616aa4323206c8971f7f4d08b9 diff --git a/src/main/scala/radiance/tile/GemminiTile.scala b/src/main/scala/radiance/tile/GemminiTile.scala index 6188d75..dcbfeb8 100644 --- a/src/main/scala/radiance/tile/GemminiTile.scala +++ b/src/main/scala/radiance/tile/GemminiTile.scala @@ -299,6 +299,10 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer) gemminiIO.ready && !ciscValid } + def gemminiBusyReg(_dReady: Bool): (Bool, UInt) = { + // (aReady, bits) + (!outer.gemmini.module.io.busy, outer.gemmini.module.io.busy.asUInt) + } outer.regNode.regmap( 0x00 -> Seq(RegField.w(32, gemminiCommandReg(_, _))), 0x10 -> Seq( @@ -307,7 +311,7 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer) 0x18 -> Seq( RegField.w(32, gemminiRs2RegLSB), RegField.w(32, gemminiRs2RegMSB)), - 0x20 -> Seq(RegField.r(32, outer.gemmini.module.io.busy)) + 0x20 -> Seq(RegField.r(32, gemminiBusyReg(_))) ) assert(!regValid || gemminiIO.ready)