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Fix sourceId collision by using a counter

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This commit is contained in:
Hansung Kim
2023-03-08 18:22:10 -08:00
parent f623cc89a7
commit a2ceb8c628
1 changed files with 11 additions and 8 deletions
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19
src/main/scala/tilelink/Coalescing.scala
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@@ -46,7 +46,7 @@ class CoalescingUnit(numThreads: Int = 1)(implicit p: Parameters)
val clientParam = Seq( val clientParam = Seq(
TLMasterParameters.v1( TLMasterParameters.v1(
name = "CoalescerNode", name = "CoalescerNode",
sourceId = IdRange(0, 1) sourceId = IdRange(0, 0xFFFF)
// visibility = Seq(AddressSet(0x0000, 0xffffff)) // visibility = Seq(AddressSet(0x0000, 0xffffff))
) )
) )
@@ -111,8 +111,7 @@ class MemTraceDriver(numThreads: Int = 1)(implicit p: Parameters)
val clientParam = Seq( val clientParam = Seq(
TLMasterParameters.v1( TLMasterParameters.v1(
name = "MemTraceDriver" + i.toString, name = "MemTraceDriver" + i.toString,
//Id range is indepdent from numThreads, IdRange determines the number of inflight reqs sourceId = IdRange(0, 0xFFFF)
sourceId = IdRange(0, 4)
// visibility = Seq(AddressSet(0x0000, 0xffffff)) // visibility = Seq(AddressSet(0x0000, 0xffffff))
) )
) )
@@ -162,6 +161,11 @@ class MemTraceDriverImp(outer: MemTraceDriver, numThreads: Int)
} }
// To prevent collision of sourceId with a current in-flight message,
// just use a counter that increments indefinitely as the sourceId of new
// messages.
val sourceIdCounter = Reg(UInt(64.W))
sourceIdCounter := sourceIdCounter + 1.U
// Connect each thread to its respective TL node. // Connect each thread to its respective TL node.
(outer.threadNodes zip threadReqs).zipWithIndex.foreach { (outer.threadNodes zip threadReqs).zipWithIndex.foreach {
@@ -173,8 +177,7 @@ class MemTraceDriverImp(outer: MemTraceDriver, numThreads: Int)
tlOut.a.bits.data := 0.U tlOut.a.bits.data := 0.U
when (req.is_store) { when (req.is_store) {
tlOut.a.bits := edge.Put( tlOut.a.bits := edge.Put(
fromSource = sourceIdCounter,
fromSource = 0.U,
toAddress = req.address, toAddress = req.address,
// 64 bits = 8 bytes = 2**(3) bytes // 64 bits = 8 bytes = 2**(3) bytes
lgSize = 3.U, lgSize = 3.U,
@@ -202,8 +205,6 @@ class MemTraceDriverImp(outer: MemTraceDriver, numThreads: Int)
dontTouch(clkcount) dontTouch(clkcount)
} }
class SimMemTrace(val filename: String, numThreads: Int) class SimMemTrace(val filename: String, numThreads: Int)
extends BlackBox( extends BlackBox(
Map("FILENAME" -> filename, "NUM_THREADS" -> numThreads) Map("FILENAME" -> filename, "NUM_THREADS" -> numThreads)
@@ -213,6 +214,8 @@ class SimMemTrace(val filename: String, numThreads: Int)
val clock = Input(Clock()) val clock = Input(Clock())
val reset = Input(Bool()) val reset = Input(Bool())
// These names have to match declarations in the Verilog code, eg.
// trace_read_address.
val trace_read = new Bundle { val trace_read = new Bundle {
val ready = Input(Bool()) val ready = Input(Bool())
val valid = Output(UInt(numThreads.W)) val valid = Output(UInt(numThreads.W))
@@ -245,7 +248,7 @@ class CoalConnectTrace(implicit p: Parameters) extends LazyModule {
val rams = Seq.tabulate(numThreads + 1) { _ => val rams = Seq.tabulate(numThreads + 1) { _ =>
LazyModule( LazyModule(
// TODO: properly propagate beatBytes? // TODO: properly propagate beatBytes?
new TLTestRAM(address = AddressSet(0x0000, 0xffffff), beatBytes = 8) new TLRAM(address = AddressSet(0x0000, 0xffffff), beatBytes = 8)
) )
} }
// Connect all (N+1) outputs of coal to separate TestRAM modules // Connect all (N+1) outputs of coal to separate TestRAM modules