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Add D data to DPI interface

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This commit is contained in:
Hansung Kim
2025-01-04 23:03:25 -08:00
parent 3af0670527
commit a4fa1522ab
3 changed files with 15 additions and 6 deletions
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9
src/main/resources/csrc/SimEmulator.cc
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@@ -6,7 +6,8 @@
extern "C" void emulator_init_rs(int num_lanes); extern "C" void emulator_init_rs(int num_lanes);
extern "C" void emulator_tick_rs(uint8_t *vec_d_ready, uint8_t *vec_d_valid, extern "C" void emulator_tick_rs(uint8_t *vec_d_ready, uint8_t *vec_d_valid,
uint8_t *vec_d_is_store, int *vec_d_size); uint8_t *vec_d_is_store, int *vec_d_size,
long long *vec_d_data);
extern "C" void emulator_generate_rs(uint8_t *vec_a_ready, uint8_t *vec_a_valid, extern "C" void emulator_generate_rs(uint8_t *vec_a_ready, uint8_t *vec_a_valid,
long long *vec_a_address, long long *vec_a_address,
uint8_t *vec_a_is_store, int *vec_a_size, uint8_t *vec_a_is_store, int *vec_a_size,
@@ -17,8 +18,10 @@ extern "C" void emulator_generate_rs(uint8_t *vec_a_ready, uint8_t *vec_a_valid,
extern "C" void emulator_init(int num_lanes) { emulator_init_rs(num_lanes); } extern "C" void emulator_init(int num_lanes) { emulator_init_rs(num_lanes); }
extern "C" void emulator_tick(uint8_t *vec_d_ready, uint8_t *vec_d_valid, extern "C" void emulator_tick(uint8_t *vec_d_ready, uint8_t *vec_d_valid,
uint8_t *vec_d_is_store, int *vec_d_size) { uint8_t *vec_d_is_store, int *vec_d_size,
emulator_tick_rs(vec_d_ready, vec_d_valid, vec_d_is_store, vec_d_size); long long *vec_d_data) {
emulator_tick_rs(vec_d_ready, vec_d_valid, vec_d_is_store, vec_d_size,
vec_d_data);
} }
extern "C" void emulator_generate(uint8_t *vec_a_ready, uint8_t *vec_a_valid, extern "C" void emulator_generate(uint8_t *vec_a_ready, uint8_t *vec_a_valid,

10
src/main/resources/vsrc/SimEmulator.v
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@@ -13,7 +13,8 @@ import "DPI-C" function void emulator_tick
output bit vec_d_ready[`MAX_NUM_LANES], output bit vec_d_ready[`MAX_NUM_LANES],
input bit vec_d_valid[`MAX_NUM_LANES], input bit vec_d_valid[`MAX_NUM_LANES],
input bit vec_d_is_store[`MAX_NUM_LANES], input bit vec_d_is_store[`MAX_NUM_LANES],
input int vec_d_size[`MAX_NUM_LANES] input int vec_d_size[`MAX_NUM_LANES],
input longint vec_d_data[`MAX_NUM_LANES]
); );
import "DPI-C" function void emulator_generate import "DPI-C" function void emulator_generate
@@ -45,8 +46,8 @@ module SimEmulator #(parameter NUM_LANES = 4) (
input [NUM_LANES-1:0] d_valid, input [NUM_LANES-1:0] d_valid,
input [NUM_LANES-1:0] d_is_store, input [NUM_LANES-1:0] d_is_store,
input [`SIMMEM_LOGSIZE_WIDTH*NUM_LANES-1:0] d_size, input [`SIMMEM_LOGSIZE_WIDTH*NUM_LANES-1:0] d_size,
input [`SIMMEM_DATA_WIDTH*NUM_LANES-1:0] d_data,
// TODO: d_mask // TODO: d_mask
// TODO: d_data
input inflight, input inflight,
output finished output finished
@@ -64,6 +65,7 @@ module SimEmulator #(parameter NUM_LANES = 4) (
bit __out_d_valid [0:`MAX_NUM_LANES-1]; bit __out_d_valid [0:`MAX_NUM_LANES-1];
bit __out_d_is_store [0:`MAX_NUM_LANES-1]; bit __out_d_is_store [0:`MAX_NUM_LANES-1];
int __out_d_size [0:`MAX_NUM_LANES-1]; int __out_d_size [0:`MAX_NUM_LANES-1];
longint __out_d_data [0:`MAX_NUM_LANES-1];
bit __out_inflight; bit __out_inflight;
bit __in_finished; bit __in_finished;
@@ -83,6 +85,7 @@ module SimEmulator #(parameter NUM_LANES = 4) (
assign __out_d_valid[g] = d_valid[g]; assign __out_d_valid[g] = d_valid[g];
assign __out_d_is_store[g] = d_is_store[g]; assign __out_d_is_store[g] = d_is_store[g];
assign __out_d_size[g] = d_size[`SIMMEM_LOGSIZE_WIDTH*g +: `SIMMEM_LOGSIZE_WIDTH]; assign __out_d_size[g] = d_size[`SIMMEM_LOGSIZE_WIDTH*g +: `SIMMEM_LOGSIZE_WIDTH];
assign __out_d_data[g] = d_data[`SIMMEM_DATA_WIDTH*g +: `SIMMEM_DATA_WIDTH];
end end
assign __out_inflight = inflight; assign __out_inflight = inflight;
endgenerate endgenerate
@@ -132,7 +135,8 @@ module SimEmulator #(parameter NUM_LANES = 4) (
__in_d_ready, __in_d_ready,
__out_d_valid, __out_d_valid,
__out_d_is_store, __out_d_is_store,
__out_d_size __out_d_size,
__out_d_data
); );
end end
end end

2
src/main/scala/radiance/core/Emulator.scala
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@@ -99,6 +99,7 @@ class EmulatorImp(
sim.io.d.valid := VecInit(laneResps.map(_.valid)).asUInt sim.io.d.valid := VecInit(laneResps.map(_.valid)).asUInt
sim.io.d.is_store := VecInit(laneResps.map(_.bits.is_store)).asUInt sim.io.d.is_store := VecInit(laneResps.map(_.bits.is_store)).asUInt
sim.io.d.size := VecInit(laneResps.map(_.bits.size)).asUInt sim.io.d.size := VecInit(laneResps.map(_.bits.size)).asUInt
sim.io.d.data := VecInit(laneResps.map(_.bits.data)).asUInt
val sourceGens = Seq.fill(numLanes)( val sourceGens = Seq.fill(numLanes)(
Module( Module(
@@ -234,6 +235,7 @@ class SimEmulator(numLanes: Int)
val valid = Input(UInt(numLanes.W)) val valid = Input(UInt(numLanes.W))
val is_store = Input(UInt(numLanes.W)) val is_store = Input(UInt(numLanes.W))
val size = Input(UInt((sizeW * numLanes).W)) val size = Input(UInt((sizeW * numLanes).W))
val data = Input(UInt((dataW * numLanes).W))
} }
}) })