get rid of monitors
This commit is contained in:
@@ -82,7 +82,25 @@ class RadianceCluster (
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val stride_by_word = true
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val stride_by_word = true
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val filter_aligned = true
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val filter_aligned = true
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val disable_monitors = false // otherwise it generate 1k+ different tl monitors
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val disable_monitors = true // otherwise it generate 1k+ different tl monitors
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def guard_monitors[T](callback: Parameters => T)(implicit p: Parameters): Unit = {
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if (disable_monitors) {
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DisableMonitors { callback }
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} else {
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callback(p)
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}
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}
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def connect_one[T <: BaseNode with TLNode](from: TLNode, to: () => T): T = {
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val t = to()
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guard_monitors { implicit p => t := from }
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t
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}
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def connect_xbar(from: TLNode): TLNode = {
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val t = TLXbar()
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guard_monitors { implicit p => t := from }
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t
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}
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val radiance_smem_fanout = radianceTiles.zipWithIndex.flatMap { case (tile, cid) =>
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val radiance_smem_fanout = radianceTiles.zipWithIndex.flatMap { case (tile, cid) =>
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tile.smemNodes.zipWithIndex.map { case (m, lid) =>
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tile.smemNodes.zipWithIndex.map { case (m, lid) =>
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@@ -156,40 +174,21 @@ class RadianceCluster (
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}
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}
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}
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}
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def connect_one[T <: BaseNode with TLNode](from: TLNode, to: () => T): T = {
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val t = to()
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if (disable_monitors) {
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DisableMonitors { implicit p => t := from}
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} else {
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t := from
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}
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t
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}
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def connect_xbar(from: TLNode): TLNode = {
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val t = TLXbar()
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if (disable_monitors) {
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DisableMonitors { implicit p => t := from}
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} else {
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t := from
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}
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t
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}
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if (stride_by_word) {
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if (stride_by_word) {
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// ask if you need to deal with this, it's not supposed to be readable
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// ask if you need to deal with this, it's not supposed to be readable
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val spad_read_nodes = Seq.fill(smem_banks) {
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val spad_read_nodes = Seq.fill(smem_banks) {
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val r_dist = DistributorNode(from = smem_width, to = wordSize)
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val r_dist = DistributorNode(from = smem_width, to = wordSize)
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r_dist := gemmini.spad_read_nodes
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guard_monitors { implicit p => r_dist := gemmini.spad_read_nodes }
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Seq.fill(smem_subbanks) { connect_one(r_dist, TLIdentityNode.apply) }
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Seq.fill(smem_subbanks) { connect_one(r_dist, TLIdentityNode.apply) }
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}
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}
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val spad_write_nodes = Seq.fill(smem_banks) {
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val spad_write_nodes = Seq.fill(smem_banks) {
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val w_dist = DistributorNode(from = smem_width, to = wordSize)
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val w_dist = DistributorNode(from = smem_width, to = wordSize)
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w_dist := gemmini.spad_write_nodes
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guard_monitors { implicit p => w_dist := gemmini.spad_write_nodes }
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Seq.fill(smem_subbanks) { connect_one(w_dist, TLIdentityNode.apply) }
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Seq.fill(smem_subbanks) { connect_one(w_dist, TLIdentityNode.apply) }
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}
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}
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val ws_dist = DistributorNode(from = smem_width, to = wordSize)
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val ws_dist = DistributorNode(from = smem_width, to = wordSize)
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ws_dist := gemmini.spad.spad_writer.node // this is the dma write node
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guard_monitors { implicit p => ws_dist := gemmini.spad.spad_writer.node } // this is the dma write node
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val spad_sp_write_nodes = Seq.fill(smem_subbanks) { connect_xbar(ws_dist) }
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val spad_sp_write_nodes = Seq.fill(smem_subbanks) { connect_xbar(ws_dist) }
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val (uniform_r_nodes, uniform_w_nodes, nonuniform_r_nodes, nonuniform_w_nodes):
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val (uniform_r_nodes, uniform_w_nodes, nonuniform_r_nodes, nonuniform_w_nodes):
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@@ -217,7 +216,20 @@ class RadianceCluster (
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}
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}
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}
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}
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val f_aligned = Seq.fill(2)(filter_nodes.map(_.map(_._1).map(connect_xbar)))
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val f_aligned = Seq.fill(2)(filter_nodes.map(_.map(_._1).map(connect_xbar)))
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val f_unaligned = Seq.fill(2)(filter_nodes.map(_.map(_._2).map(connect_xbar)))
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// val f_unaligned = Seq.fill(2)(filter_nodes.map(_.map(_._2).map(connect_xbar)))
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val f_unaligned = Seq.fill(2) {
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val serialized_node = TLEphemeralNode()
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val serialized_in_xbar = TLXbar()
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val serialized_out_xbar = TLXbar()
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guard_monitors { implicit p =>
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filter_nodes.foreach(_.map(_._2).foreach(serialized_in_xbar := _))
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serialized_node := serialized_in_xbar
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serialized_out_xbar := serialized_node
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}
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Seq(serialized_out_xbar)
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}
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val uniform_r_nodes: Seq[Seq[Seq[TLNode]]] = spad_read_nodes.map { rb =>
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val uniform_r_nodes: Seq[Seq[Seq[TLNode]]] = spad_read_nodes.map { rb =>
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(rb zip f_aligned.head).map { case (rw, fa) => Seq(rw) ++ fa }
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(rb zip f_aligned.head).map { case (rw, fa) => Seq(rw) ++ fa }
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@@ -229,7 +241,7 @@ class RadianceCluster (
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}
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}
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// all to all xbar
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// all to all xbar
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val Seq(nonuniform_r_nodes, nonuniform_w_nodes) = f_unaligned.map(_.flatten)
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val Seq(nonuniform_r_nodes, nonuniform_w_nodes) = f_unaligned // f_unaligned.map(_.flatten)
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(uniform_r_nodes, uniform_w_nodes, nonuniform_r_nodes, nonuniform_w_nodes)
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(uniform_r_nodes, uniform_w_nodes, nonuniform_r_nodes, nonuniform_w_nodes)
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} else {
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} else {
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@@ -248,7 +260,7 @@ class RadianceCluster (
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(uniform_r_nodes, uniform_w_nodes, nonuniform_r_nodes, nonuniform_w_nodes)
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(uniform_r_nodes, uniform_w_nodes, nonuniform_r_nodes, nonuniform_w_nodes)
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}
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}
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radiance_smem_fanout.foreach(clbus.inwardNode := _)
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guard_monitors { implicit p => radiance_smem_fanout.foreach(clbus.inwardNode := _) }
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smem_bank_mgrs.grouped(smem_subbanks).zipWithIndex.foreach { case (bank_mgrs, bid) =>
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smem_bank_mgrs.grouped(smem_subbanks).zipWithIndex.foreach { case (bank_mgrs, bid) =>
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bank_mgrs.zipWithIndex.foreach { case (Seq(r, w), wid) =>
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bank_mgrs.zipWithIndex.foreach { case (Seq(r, w), wid) =>
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@@ -256,7 +268,7 @@ class RadianceCluster (
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val subbank_r_xbar = TLXbar(TLArbiter.lowestIndexFirst)
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val subbank_r_xbar = TLXbar(TLArbiter.lowestIndexFirst)
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val subbank_w_xbar = TLXbar(TLArbiter.lowestIndexFirst)
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val subbank_w_xbar = TLXbar(TLArbiter.lowestIndexFirst)
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def connect_smem_banks(): Unit = {
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guard_monitors { implicit p =>
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r := subbank_r_xbar
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r := subbank_r_xbar
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w := subbank_w_xbar
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w := subbank_w_xbar
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uniform_r_nodes(bid)(wid).foreach( subbank_r_xbar := _ )
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uniform_r_nodes(bid)(wid).foreach( subbank_r_xbar := _ )
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@@ -265,12 +277,6 @@ class RadianceCluster (
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nonuniform_r_nodes.foreach( subbank_r_xbar := _ )
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nonuniform_r_nodes.foreach( subbank_r_xbar := _ )
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nonuniform_w_nodes.foreach( subbank_w_xbar := _ )
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nonuniform_w_nodes.foreach( subbank_w_xbar := _ )
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}
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}
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if (disable_monitors) {
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DisableMonitors(_ => connect_smem_banks())
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} else {
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connect_smem_banks()
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}
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}
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}
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}
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}
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} else {
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} else {
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