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move virgo components into shared mem module, more cleanup

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This commit is contained in:
Richard Yan
2024-09-26 14:41:46 -07:00
parent 998f73b54a
commit f11385218f
4 changed files with 38 additions and 38 deletions
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50
src/main/scala/radiance/memory/AlignFilterNode.scala
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@@ -20,21 +20,21 @@ class AlignFilterNode(filters: Seq[AddressSet])(implicit p: Parameters) extends
s"found ${seq.map(_.masters.size).sum}") s"found ${seq.map(_.masters.size).sum}")
val master = seq.head.masters.head val master = seq.head.masters.head
val in_mapping = TLXbar.mapInputIds(Seq.fill(filters.length + 1)(seq.head)) val inMapping = TLXbar.mapInputIds(Seq.fill(filters.length + 1)(seq.head))
val unaligned_src_range = in_mapping.last val unalignedSrcRange = inMapping.last
seq.head.v1copy( seq.head.v1copy(
clients = filters.zipWithIndex.map { case (filter, i) => clients = filters.zipWithIndex.map { case (filter, i) =>
master.v2copy( master.v2copy(
name = s"${name}_filter_aligned", name = s"${name}_filter_aligned",
sourceId = in_mapping(i), sourceId = inMapping(i),
visibility = Seq(filter), visibility = Seq(filter),
emits = seq.map(_.anyEmitClaims).reduce(_ mincover _) emits = seq.map(_.anyEmitClaims).reduce(_ mincover _)
) )
} ++ Seq( } ++ Seq(
master.v2copy( master.v2copy(
name = s"${name}_filter_unaligned", name = s"${name}_filter_unaligned",
sourceId = unaligned_src_range, sourceId = unalignedSrcRange,
visibility = Seq(AddressSet.everything), visibility = Seq(AddressSet.everything),
emits = seq.map(_.anyEmitClaims).reduce(_ mincover _) emits = seq.map(_.anyEmitClaims).reduce(_ mincover _)
), ),
@@ -58,46 +58,46 @@ class AlignFilterNode(filters: Seq[AddressSet])(implicit p: Parameters) extends
) )
}) })
def cast_d[T <: TLBundleD](d: TLBundleD, target_d_t: T): T = { def castD[T <: TLBundleD](d: TLBundleD, targetDType: T): T = {
val new_d = Wire(target_d_t.cloneType) val newD = Wire(targetDType.cloneType)
d.elements.foreach { case (name, data) => d.elements.foreach { case (name, data) =>
val new_d_field = new_d.elements.filter(_._1 == name).head._2 val newDField = newD.elements.filter(_._1 == name).head._2
new_d_field := data.asTypeOf(new_d_field) newDField := data.asTypeOf(newDField)
} }
new_d newD
} }
def cast_d[T <: DecoupledIO[TLBundleD]](ds: Seq[DecoupledIO[TLBundleD]], target_d_t: T): Seq[T] = { def castD[T <: DecoupledIO[TLBundleD]](ds: Seq[DecoupledIO[TLBundleD]], targetDType: T): Seq[T] = {
ds.map { d => ds.map { d =>
val new_d = Wire(target_d_t.cloneType) val newD = Wire(targetDType.cloneType)
new_d.valid := d.valid newD.valid := d.valid
new_d.bits := cast_d(d.bits, target_d_t.bits) newD.bits := castD(d.bits, targetDType.bits)
d.ready := new_d.ready d.ready := newD.ready
new_d newD
} }
} }
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val (c, c_edge) = node.in.head val (c, cEdge) = node.in.head
val a = node.out.init.map(_._1) val a = node.out.init.map(_._1)
val ua = node.out.last._1 val ua = node.out.last._1
val in_mapping = TLXbar.mapInputIds(Seq.fill(filters.length + 1)(node.in.head._2.client)) val inMapping = TLXbar.mapInputIds(Seq.fill(filters.length + 1)(node.in.head._2.client))
val unaligned_src = in_mapping.last val unalignedSrc = inMapping.last
val a_aligned = filters.map(_.contains(c.a.bits.address)) val aAligned = filters.map(_.contains(c.a.bits.address))
(a zip a_aligned).zipWithIndex.foreach { case ((a, aligned), idx) => (a zip aAligned).zipWithIndex.foreach { case ((a, aligned), idx) =>
a.a.bits := c.a.bits a.a.bits := c.a.bits
a.a.bits.source := in_mapping(idx).start.U + c.a.bits.source a.a.bits.source := inMapping(idx).start.U + c.a.bits.source
a.a.valid := c.a.valid && aligned a.a.valid := c.a.valid && aligned
} }
ua.a.bits := c.a.bits ua.a.bits := c.a.bits
ua.a.bits.source := unaligned_src.start.U + c.a.bits.source // + (1.U << c.a.bits.source.getWidth) ua.a.bits.source := unalignedSrc.start.U + c.a.bits.source // + (1.U << c.a.bits.source.getWidth)
ua.a.valid := c.a.valid && !a_aligned.reduce(_ || _) ua.a.valid := c.a.valid && !aAligned.reduce(_ || _)
c.a.ready := MuxCase(ua.a.ready, (a zip a_aligned).map { case (a, aligned) => aligned -> a.a.ready }) c.a.ready := MuxCase(ua.a.ready, (a zip aAligned).map { case (a, aligned) => aligned -> a.a.ready })
TLArbiter.robin(c_edge, c.d, cast_d(a.map(_.d) ++ Seq(ua.d), c.d): _*) TLArbiter.robin(cEdge, c.d, castD(a.map(_.d) ++ Seq(ua.d), c.d): _*)
} }
} }

10
src/main/scala/radiance/memory/DistributorNode.scala
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@@ -14,14 +14,14 @@ import org.chipsalliance.diplomacy.lazymodule._
class DistributorNode(from: Int, to: Int)(implicit p: Parameters) extends LazyModule { class DistributorNode(from: Int, to: Int)(implicit p: Parameters) extends LazyModule {
require(isPow2(from) && isPow2(to) && (from >= to), "invalid distributor node parameters") require(isPow2(from) && isPow2(to) && (from >= to), "invalid distributor node parameters")
println(s"distributor node to segment from $from into $to") println(s"distributor node to segment from $from into $to")
val num_clients = from / to val numClients = from / to
val node = TLNexusNode(clientFn = seq => { val node = TLNexusNode(clientFn = seq => {
require(seq.map(_.masters.size).sum == 1, s"there should only be one client to a distributor node, found ${seq.map(_.masters.size).sum}") require(seq.map(_.masters.size).sum == 1, s"there should only be one client to a distributor node, found ${seq.map(_.masters.size).sum}")
val master = seq.head.masters.head val master = seq.head.masters.head
require(isPow2(master.sourceId.size)) require(isPow2(master.sourceId.size))
seq.head.v1copy( seq.head.v1copy(
clients = Seq.tabulate(num_clients)(i => master.v2copy( clients = Seq.tabulate(numClients)(i => master.v2copy(
name = s"${name}_dist_client_$i", name = s"${name}_dist_client_$i",
emits = TLMasterToSlaveTransferSizes( emits = TLMasterToSlaveTransferSizes(
get = TransferSizes(to, to), get = TransferSizes(to, to),
@@ -55,7 +55,7 @@ class DistributorNode(from: Int, to: Int)(implicit p: Parameters) extends LazyMo
val cn = node.in.head._1 val cn = node.in.head._1
val mn = node.out.map(_._1) val mn = node.out.map(_._1)
println(f"$name node in size ${node.in.size}, out size ${node.out.size}") println(f"$name node in size ${node.in.size}, out size ${node.out.size}")
assert(node.out.size == num_clients, s"got ${node.out.size} clients instead of $num_clients") assert(node.out.size == numClients, s"got ${node.out.size} clients instead of $numClients")
// A channel // A channel
val ca = cn.a.bits val ca = cn.a.bits
@@ -64,7 +64,7 @@ class DistributorNode(from: Int, to: Int)(implicit p: Parameters) extends LazyMo
m.opcode := ca.opcode m.opcode := ca.opcode
m.param := ca.param m.param := ca.param
m.user := ca.user m.user := ca.user
m.source := Cat(i.U(log2Ceil(num_clients).W), ca.source) m.source := Cat(i.U(log2Ceil(numClients).W), ca.source)
m.address := ca.address + (to * i).U m.address := ca.address + (to * i).U
m.mask := ca.mask((i + 1) * to - 1, i * to) m.mask := ca.mask((i + 1) * to - 1, i * to)
m.data := ca.data((i + 1) * to * 8 - 1, i * to * 8) m.data := ca.data((i + 1) * to * 8 - 1, i * to * 8)
@@ -77,7 +77,7 @@ class DistributorNode(from: Int, to: Int)(implicit p: Parameters) extends LazyMo
val cd = cn.d.bits val cd = cn.d.bits
cd.size := log2Ceil(from).U cd.size := log2Ceil(from).U
val partialWait = RegInit(false.B) val partialWait = RegInit(false.B)
val arrived = RegInit(0.U(num_clients.W)) val arrived = RegInit(0.U(numClients.W))
val cdReg = RegInit(0.U.asTypeOf(cd.cloneType)) val cdReg = RegInit(0.U.asTypeOf(cd.cloneType))
def setMetadata(to: TLBundleD, from: TLBundleD): Unit = { def setMetadata(to: TLBundleD, from: TLBundleD): Unit = {

9
src/main/scala/radiance/tile/RadianceCluster.scala
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@@ -32,18 +32,17 @@ class RadianceCluster (
crossing: ClockCrossingType, crossing: ClockCrossingType,
lookup: LookupByClusterIdImpl lookup: LookupByClusterIdImpl
)(implicit p: Parameters) extends Cluster(thisClusterParams, crossing, lookup) { )(implicit p: Parameters) extends Cluster(thisClusterParams, crossing, lookup) {
val smemKey = p(RadianceSharedMemKey).get
val numCoresInCluster = leafTiles.size - gemminiTiles.size
// make the shared memory srams and interconnects // make the shared memory srams and interconnects
val gemminiTiles = leafTiles.values.filter(_.isInstanceOf[GemminiTile]).toSeq.asInstanceOf[Seq[GemminiTile]] val gemminiTiles = leafTiles.values.filter(_.isInstanceOf[GemminiTile]).toSeq.asInstanceOf[Seq[GemminiTile]]
val radianceTiles = leafTiles.values.filter(_.isInstanceOf[RadianceTile]).toSeq.asInstanceOf[Seq[RadianceTile]] val radianceTiles = leafTiles.values.filter(_.isInstanceOf[RadianceTile]).toSeq.asInstanceOf[Seq[RadianceTile]]
// TODO: this probably needs to be instantiated inside the radiance shared mem module // TODO: this probably needs to be instantiated inside the radiance shared mem module
val virgoSharedMemComponents = new VirgoSharedMemComponents(thisClusterParams, gemminiTiles, radianceTiles) def virgoSharedMemComponentsGen() = new VirgoSharedMemComponents(thisClusterParams, gemminiTiles, radianceTiles)
LazyModule(new RadianceSharedMem(virgoSharedMemComponents, clbus)).suggestName("shared_mem") LazyModule(new RadianceSharedMem(virgoSharedMemComponentsGen, clbus)).suggestName("shared_mem")
// direct core-accelerator connections // direct core-accelerator connections
val smemKey = p(RadianceSharedMemKey).get
val numCoresInCluster = leafTiles.size - gemminiTiles.size
val radianceAccSlaveNodes = Seq.fill(numCoresInCluster)(AccSlaveNode()) val radianceAccSlaveNodes = Seq.fill(numCoresInCluster)(AccSlaveNode())
(radianceAccSlaveNodes zip radianceTiles).foreach { case (a, r) => a := r.accMasterNode } (radianceAccSlaveNodes zip radianceTiles).foreach { case (a, r) => a := r.accMasterNode }
val gemminiAccMasterNodes = gemminiTiles.map { tile => val gemminiAccMasterNodes = gemminiTiles.map { tile =>

7
src/main/scala/radiance/tile/RadianceSharedMem.scala
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@@ -20,7 +20,7 @@ trait RadianceSmemNodeProvider {
} }
class RadianceSharedMem( class RadianceSharedMem(
provider: RadianceSmemNodeProvider, provider: () => RadianceSmemNodeProvider,
clbus: TLBusWrapper clbus: TLBusWrapper
)(implicit p: Parameters) extends LazyModule { )(implicit p: Parameters) extends LazyModule {
val smemKey = p(RadianceSharedMemKey).get val smemKey = p(RadianceSharedMemKey).get
@@ -34,8 +34,9 @@ class RadianceSharedMem(
require(isPow2(smemBanks)) require(isPow2(smemBanks))
val smNodes = provider()
val (uniformRNodes, uniformWNodes, nonuniformRNodes, nonuniformWNodes) = val (uniformRNodes, uniformWNodes, nonuniformRNodes, nonuniformWNodes) =
(provider.uniformRNodes, provider.uniformWNodes, provider.nonuniformRNodes, provider.nonuniformWNodes) (smNodes.uniformRNodes, smNodes.uniformWNodes, smNodes.nonuniformRNodes, smNodes.nonuniformWNodes)
// TODO: move this to config // TODO: move this to config
val strideByWord = true val strideByWord = true
@@ -174,7 +175,7 @@ class RadianceSharedMem(
} }
} // stride by word } // stride by word
guardMonitors { implicit p => provider.clBusClients.foreach(clbus.inwardNode := _) } guardMonitors { implicit p => smNodes.clBusClients.foreach(clbus.inwardNode := _) }
lazy val module = new RadianceSharedMemImp(this) lazy val module = new RadianceSharedMemImp(this)
} }