diff --git a/src/main/scala/radiance/memory/AddressRewriterNode.scala b/src/main/scala/radiance/memory/AddressRewriterNode.scala
new file mode 100644
index 0000000..82723bb
--- /dev/null
+++ b/src/main/scala/radiance/memory/AddressRewriterNode.scala
@@ -0,0 +1,27 @@
+package radiance.memory
+
+import chisel3._
+import chisel3.util._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink.TLAdapterNode
+import org.chipsalliance.cde.config.Parameters
+
+
+class AddressRewriterNode(baseAddr: BigInt)(implicit p: Parameters) extends LazyModule {
+  require(isPow2(baseAddr), "base address must be a power of 2")
+
+  val node = TLAdapterNode(clientFn = c => c, managerFn = m => m)
+  val module = new LazyModuleImp(this) {
+    (node.in.map(_._1) zip node.out.map(_._1)).foreach { case (i, o) =>
+      o.a <> i.a
+      o.a.bits.address := i.a.bits.address | baseAddr.U
+      i.d <> o.d
+    }
+  }
+}
+
+object AddressRewriterNode {
+  def apply(baseAddr: BigInt)(implicit p: Parameters): TLAdapterNode = {
+    new AddressRewriterNode(baseAddr).node
+  }
+}
\ No newline at end of file
diff --git a/src/main/scala/radiance/subsystem/Configs.scala b/src/main/scala/radiance/subsystem/Configs.scala
index 96ec6fb..536e35b 100644
--- a/src/main/scala/radiance/subsystem/Configs.scala
+++ b/src/main/scala/radiance/subsystem/Configs.scala
@@ -172,3 +172,14 @@ class WithNCustomSmallRocketCores(
     )) ++ prev
   }
 })
+
+class WithExtGPUMem(address: BigInt = BigInt("0x100000000", 16),
+                    size: BigInt = 0x80000000) extends Config((site, here, up) => {
+  case GPUMemory() => Some(GPUMemParams(address, size))
+  case ExtMem => up(ExtMem, site).map(x => {
+    val gap = address - x.master.base - x.master.size
+    x.copy(master = x.master.copy(size = x.master.size + gap + size))
+  })
+})
+case class GPUMemParams(address: BigInt = BigInt("0x100000000", 16), size: BigInt = 0x80000000)
+case class GPUMemory() extends Field[Option[GPUMemParams]](None)
\ No newline at end of file
diff --git a/src/main/scala/radiance/tile/VortexTile.scala b/src/main/scala/radiance/tile/VortexTile.scala
index d7bc3fe..86e15f4 100644
--- a/src/main/scala/radiance/tile/VortexTile.scala
+++ b/src/main/scala/radiance/tile/VortexTile.scala
@@ -18,6 +18,7 @@ import freechips.rocketchip.regmapper.RegField
 import freechips.rocketchip.tile._
 import radiance.memory._
 import gemmini.{Gemmini, GemminiCustomConfigs}
+import radiance.subsystem.{GPUMemParams, GPUMemory}
 
 case class VortexTileParams(
     core: VortexCoreParams = VortexCoreParams(),
@@ -334,20 +335,26 @@ class VortexTile private (
   smemNodes.foreach(smemXbar.node := _)
   // smemBanks.foreach(_.node := smemXbar.node)
 
+  val base = p(GPUMemory()) match {
+    case Some(GPUMemParams(baseAddr, _)) => baseAddr
+    case _ => BigInt(0)
+  }
+
   if (vortexParams.useVxCache) {
-    tlMasterXbar.node := TLWidthWidget(16) := memNode
+    tlMasterXbar.node := AddressRewriterNode(base) := TLWidthWidget(16) := memNode
   } else {
     // imemNodes.foreach { tlMasterXbar.node := TLWidthWidget(4) := _ }
-    tlMasterXbar.node :=* icacheNode
-    tlMasterXbar.node :=* dcacheNode
+    tlMasterXbar.node :=* AddressRewriterNode(base) :=* icacheNode
+    tlMasterXbar.node :=* AddressRewriterNode(base) :=* dcacheNode
   }
 
+
   // ROCC
   // TODO: parametrize
   val gemmini = LazyModule(new Gemmini(GemminiCustomConfigs.unifiedMemConfig))
   val roccs: Seq[LazyRoCC] = Seq(gemmini)
-  tlMasterXbar.node :=* gemmini.atlNode
-  tlOtherMastersNode :=* gemmini.tlNode
+  tlMasterXbar.node :=* AddressRewriterNode(base) :=* gemmini.atlNode
+  tlOtherMastersNode :=* AddressRewriterNode(base) :=* gemmini.tlNode
 
   gemmini.stlNode :=* TLWidthWidget(4) :=* smemXbar.node
   gemmini.unified_mem_node :=* TLWidthWidget(4) :=* smemXbar.node