Hansung Kim
41ecf6bc20
Squelch debug prints in SimMemTrace
2023-03-07 17:53:09 -08:00
Hansung Kim
1bc8cbb925
Instantiate FIFOs to buffer TL reqs per each lane
2023-03-07 15:10:00 -08:00
Hansung Kim
337272764b
Test with Get() and doc source ID allocation
2023-03-06 23:15:30 -08:00
Hansung Kim
760d3f5aa2
Add example where IdentityNode.out has different data from .in
2023-03-06 21:56:56 -08:00
Hansung Kim
c7651e26f4
Organize Diplomacy node structure of CoalescingUnit
...
IdentityNode with numThreads edges + master TL node with additional 1
edge for the new coalesced requests.
2023-03-06 16:17:52 -08:00
Hansung Kim
aa2d52a197
Merge Coalescing{Logic, Entry} to CoalescingUnit
...
CoalescingUnit acts as the top module that abstracts TL wrangling away
from outside.
2023-03-05 17:33:37 -08:00
Hansung Kim
6fea4be050
Refactor with zip
2023-03-05 16:59:06 -08:00
Hansung Kim
db9be56191
Properly connect each lane to TL node
2023-03-05 00:18:29 -08:00
Hansung Kim
ef1608505f
Use single SimMemTrace instance
2023-03-04 23:55:20 -08:00
Hansung Kim
172ab51355
Fix formatting and unused warnings
2023-03-03 23:44:50 -08:00
Hansung Kim
5f55a7578f
Recover lost changes
2023-03-03 22:36:54 -08:00
Hansung Kim
dcb49f7683
Doc update
2023-03-03 21:22:56 -08:00
Vamber Yang
1a322f5ca7
Merge remote-tracking branch 'origin/graphics' into HEAD
...
Pulling remote changes before pushing
2023-03-03 20:40:41 -08:00
Vamber Yang
c3129b8c5c
Tracer supports N threads, communicates with Coalescing with TL + Diplomacy interface
2023-03-03 20:27:29 -08:00
Hansung Kim
97fec01620
Receive per-lane valid from SimMemTrace
2023-03-03 18:09:58 -08:00
Hansung Kim
c1e8f4ef86
Maintain cycle inside Verilog instead of C
...
The Verilog wrapper maintains the cycle state, and C parser becomes a
combinational logic which Verilog queries to check if there is a request
in the trace at a specific {cycle, core_id, thread_id}.
2023-03-03 16:38:32 -08:00
Hansung Kim
664959f723
Parameterize SimMemTrace Verilog module to number of threads
2023-03-03 16:16:07 -08:00
Hansung Kim
44cf6fbb2f
Update SimMemTrace csrc from submodule
2023-03-03 16:14:11 -08:00
Hansung Kim
b57c0e2b7d
SimMemTrace: parse batch instead of at every cycle
2023-03-02 17:24:36 -08:00
Hansung Kim
24f4ee93ac
Add TL client node to MemTraceDriver
2023-02-27 23:35:14 -08:00
Hansung Kim
a06b5faa3c
Wrap memtrace DPI module with a Chisel driver module
2023-02-27 19:55:22 -08:00
Hansung Kim
9025729c0e
Emit address in addition to cycle
2023-02-27 17:36:54 -08:00
Hansung Kim
0ebaed5f1b
Communicate trace cycle data from C++ to Chisel
2023-02-27 14:40:49 -08:00
Hansung Kim
72de4bca66
Initial parsing of memory trace file in C++
2023-02-27 13:47:30 -08:00
Hansung Kim
80e4b5c734
Set up simple DPI for trace-driven testing
2023-02-26 20:39:19 -08:00
Hansung Kim
5bf8bb8217
Add empty unit test for coalescing unit
...
copied over from WithTLXbarUnitTests
2023-02-22 16:42:18 -08:00
Huy Vo
1b733e7cf0
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-03-13 12:34:39 -07:00
Andrew Waterman
2607153b67
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-03-09 02:08:55 -08:00
Yunsup Lee
4f00bcc760
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-29 17:12:02 -08:00
Huy Vo
0fd777f480
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-26 17:24:23 -08:00
Andrew Waterman
71c8d3fd41
reorganize directory structure
2012-02-08 15:13:08 -08:00
