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a06911cf5b33727e1a12ede02db5db37c3d6c65d
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47 Commits

Author SHA1 Message Date
Hansung Kim
a06911cf5b Make response queue, debug print for inflight entry 2023-03-26 01:07:53 -07:00
Hansung Kim
356aa9079f Make table RAM, not CAM 2023-03-23 21:16:05 -07:00
Hansung Kim
9f5b77145b Change inflight table entry to per-lane and per-srcId 2023-03-19 02:08:17 -07:00
Hansung Kim
08ce7dc57d Doc cleanup 2023-03-19 01:17:11 -07:00
Hansung Kim
2e06898dc0 Handle enqueue and lookup at the same cycle 
This fixes the inflight table filling up to full after some time in the
memtrace simulation.
 2023-03-13 16:22:22 -07:00
Hansung Kim
cb8ca183d5 Add debug counter for per-lane inflight reqs 2023-03-13 15:37:52 -07:00
Hansung Kim
400b356cfb Fix lookup succeeding on invalid entry; add test case 
also enable VCS FSDB annotation in chiseltest
 2023-03-12 03:26:09 -07:00
Hansung Kim
6de95587de Add chiseltest for inflight table 2023-03-11 23:20:50 -08:00
Hansung Kim
df0c2ba89f Flip lookup signal flow 
'ready' is now an input port that an external module uses to initiate
lookup, and 'valid' and 'bits' send the match result and table entry
back to the outside.  So far that's similar to a dequeue, but since we
also need to receive a sourceId key for the lookup, make a new input
port alongside the r/v interface.  Feels a little hacky but works for
now.
 2023-03-10 19:15:08 -08:00
Hansung Kim
2ba03fc16d Write sourceId lookup logic for table 2023-03-10 18:32:15 -08:00
Hansung Kim
3887129994 Write enqueue and reset logic for table 2023-03-10 18:00:38 -08:00
Hansung Kim
9256b8f6a3 Write simple next-empty-entry finding logic 2023-03-10 17:27:04 -08:00
Hansung Kim
6866b537d6 Separate out InflightCoalReqTable into a module 2023-03-10 15:28:28 -08:00
Hansung Kim
da58ab552f Construct entry for in-flight coalesced requests table 2023-03-10 14:22:43 -08:00
Hansung Kim
93b198e0f6 Properly assert ready/valid for all TL channels 2023-03-10 00:22:38 -08:00
Hansung Kim
e523b4235a Make placeholder for inflight coalesced request table 2023-03-09 23:48:12 -08:00
Hansung Kim
13552593c8 Check legal from Get and Put 2023-03-09 22:56:34 -08:00
Hansung Kim
46d3109e82 Skip instantiating queue for the edge from master node 2023-03-09 22:39:49 -08:00
Hansung Kim
9bfb813e1b Thread -> Lane 
"thread" is confusing, unify to lane when denoting a hardware SIMD lane
inside a single warp.
 2023-03-09 22:09:21 -08:00
Hansung Kim
a495149869 Connect coal master node to identitynode internally 
Instead of exposing master node to downstream, wrap everything inside
the IdentityNode with N+1:N+1 edges. The inward edges exposed to the
upstream nodes are only N edges. Needs more testing.
 2023-03-09 20:53:52 -08:00
Hansung Kim
f0069ba3ad Set lgSize=0 as memtrace addresses are not aligned 
This is TODO, we need to have a logic inside MemTraceDriver that aligns
these addresses to word boundaries and sets the right masks, similar to
how an actual core issues load/stores.
 2023-03-09 20:50:34 -08:00
Hansung Kim
babbdf9550 Left out fromSource 2023-03-08 18:36:47 -08:00
Hansung Kim
70b715645c Parameterize sourceId width for reg entry 2023-03-08 18:32:06 -08:00
Hansung Kim
a2ceb8c628 Fix sourceId collision by using a counter 2023-03-08 18:31:03 -08:00
Vamber Yang
f623cc89a7 Merged with origin/graphics, MemTracer able to read and write according to tracefile 2023-03-08 17:38:59 -08:00
Vamber Yang
0de09daa05 MemTracer able to read and write according to trace file, also support thread_id skipping in trace file 2023-03-08 17:34:10 -08:00
Hansung Kim
39db60f42b Queue -> ShiftQueue, preserve source id of incoming reqs 2023-03-08 16:49:36 -08:00
Hansung Kim
41ecf6bc20 Squelch debug prints in SimMemTrace 2023-03-07 17:53:09 -08:00
Hansung Kim
1bc8cbb925 Instantiate FIFOs to buffer TL reqs per each lane 2023-03-07 15:10:00 -08:00
Hansung Kim
337272764b Test with Get() and doc source ID allocation 2023-03-06 23:15:30 -08:00
Hansung Kim
760d3f5aa2 Add example where IdentityNode.out has different data from .in 2023-03-06 21:56:56 -08:00
Hansung Kim
c7651e26f4 Organize Diplomacy node structure of CoalescingUnit 
IdentityNode with numThreads edges + master TL node with additional 1
edge for the new coalesced requests.
 2023-03-06 16:17:52 -08:00
Hansung Kim
aa2d52a197 Merge Coalescing{Logic, Entry} to CoalescingUnit 
CoalescingUnit acts as the top module that abstracts TL wrangling away
from outside.
 2023-03-05 17:33:37 -08:00
Hansung Kim
6fea4be050 Refactor with zip 2023-03-05 16:59:06 -08:00
Hansung Kim
db9be56191 Properly connect each lane to TL node 2023-03-05 00:18:29 -08:00
Hansung Kim
ef1608505f Use single SimMemTrace instance 2023-03-04 23:55:20 -08:00
Hansung Kim
172ab51355 Fix formatting and unused warnings 2023-03-03 23:44:50 -08:00
Hansung Kim
5f55a7578f Recover lost changes 2023-03-03 22:36:54 -08:00
Hansung Kim
dcb49f7683 Doc update 2023-03-03 21:22:56 -08:00
Vamber Yang
c3129b8c5c Tracer supports N threads, communicates with Coalescing with TL + Diplomacy interface 2023-03-03 20:27:29 -08:00
Hansung Kim
24f4ee93ac Add TL client node to MemTraceDriver 2023-02-27 23:35:14 -08:00
Hansung Kim
a06b5faa3c Wrap memtrace DPI module with a Chisel driver module 2023-02-27 19:55:22 -08:00
Hansung Kim
9025729c0e Emit address in addition to cycle 2023-02-27 17:36:54 -08:00
Hansung Kim
0ebaed5f1b Communicate trace cycle data from C++ to Chisel 2023-02-27 14:40:49 -08:00
Hansung Kim
72de4bca66 Initial parsing of memory trace file in C++ 2023-02-27 13:47:30 -08:00
Hansung Kim
80e4b5c734 Set up simple DPI for trace-driven testing 2023-02-26 20:39:19 -08:00
Hansung Kim
5bf8bb8217 Add empty unit test for coalescing unit 
copied over from WithTLXbarUnitTests
 2023-02-22 16:42:18 -08:00