Hansung Kim
97fec01620
Receive per-lane valid from SimMemTrace
2023-03-03 18:09:58 -08:00
Hansung Kim
c1e8f4ef86
Maintain cycle inside Verilog instead of C
...
The Verilog wrapper maintains the cycle state, and C parser becomes a
combinational logic which Verilog queries to check if there is a request
in the trace at a specific {cycle, core_id, thread_id}.
2023-03-03 16:38:32 -08:00
Hansung Kim
664959f723
Parameterize SimMemTrace Verilog module to number of threads
2023-03-03 16:16:07 -08:00
Hansung Kim
44cf6fbb2f
Update SimMemTrace csrc from submodule
2023-03-03 16:14:11 -08:00
Hansung Kim
b57c0e2b7d
SimMemTrace: parse batch instead of at every cycle
2023-03-02 17:24:36 -08:00
Hansung Kim
24f4ee93ac
Add TL client node to MemTraceDriver
2023-02-27 23:35:14 -08:00
Hansung Kim
a06b5faa3c
Wrap memtrace DPI module with a Chisel driver module
2023-02-27 19:55:22 -08:00
Hansung Kim
9025729c0e
Emit address in addition to cycle
2023-02-27 17:36:54 -08:00
Hansung Kim
0ebaed5f1b
Communicate trace cycle data from C++ to Chisel
2023-02-27 14:40:49 -08:00
Hansung Kim
72de4bca66
Initial parsing of memory trace file in C++
2023-02-27 13:47:30 -08:00
Hansung Kim
80e4b5c734
Set up simple DPI for trace-driven testing
2023-02-26 20:39:19 -08:00
Hansung Kim
5bf8bb8217
Add empty unit test for coalescing unit
...
copied over from WithTLXbarUnitTests
2023-02-22 16:42:18 -08:00
Huy Vo
1b733e7cf0
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-03-13 12:34:39 -07:00
Andrew Waterman
2607153b67
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-03-09 02:08:55 -08:00
Yunsup Lee
4f00bcc760
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-29 17:12:02 -08:00
Huy Vo
0fd777f480
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-26 17:24:23 -08:00
Andrew Waterman
71c8d3fd41
reorganize directory structure
2012-02-08 15:13:08 -08:00
