load_package flow


set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
set_global_assignment -name SDC_FILE vortex.sdc
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL

# pins configuration
package require cmdline

proc make_all_pins_virtual { args } {

    set options {\
        { "exclude.arg" "" "List of signals to exclude" } \
    }
    array set opts [::cmdline::getoptions quartus(args) $options]

    remove_all_instance_assignments -name VIRTUAL_PIN
    execute_module -tool map
    set name_ids [get_names -filter * -node_type pin]

    foreach_in_collection name_id $name_ids {
        set pin_name [get_name_info -info full_path $name_id]

        if { -1 == [lsearch -exact $opts(excludes) $pin_name] } {
            post_message "Making VIRTUAL_PIN assignment to $pin_name"
            set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
        } else {
            post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
        }
    }
    export_assignments
}


make_all_pins_virtual -exclude { clk, reset }