{
    "version": 1,
    "includes":[
        "../rtl/VX_config.vh", 
        "../rtl/VX_platform.vh", 
        "../rtl/VX_define.vh", 
        "../rtl/cache/VX_cache_config.vh"
    ],
    "modules": {
        "afu": {            
            "submodules": {
                "vortex": {"type":"Vortex", "enabled":true}
            }
        },
        "Vortex": {
            "submodules": {
                "cluster": {"type":"VX_cluster", "count":"`NUM_CLUSTERS"},
                "l3cache": {"type":"VX_cache", "enabled":"`L3_ENABLE", "params":{"NUM_BANKS":"`L3NUM_BANKS"}}
            }
        },
        "VX_cluster": {
            "submodules": {
                "core": {"type":"VX_core", "count":"`NUM_CORES", "enabled":true},
                "l2cache": {"type":"VX_cache", "enabled":"`L2_ENABLE", "params":{"NUM_BANKS":"`L2NUM_BANKS"}}
            }
        },
        "VX_core": {
            "submodules": {
                "pipeline": {"type":"VX_pipeline", "enabled":true},
                "mem_unit": {"type":"VX_mem_unit", "enabled":true}
            }
        },
        "VX_pipeline": {
            "submodules": {
                "fetch": {"type":"VX_fetch", "enabled":true},
                "decode": {"type":"VX_decode", "enabled":true},
                "issue": {"type":"VX_issue", "enabled":true},
                "execute": {"type":"VX_execute", "enabled":true},
                "commit": {"type":"VX_commit", "enabled":true}
            }
        },
        "VX_fetch": {            
            "submodules": {
                "warp_sched": {"type":"VX_warp_sched"},
                "icache_stage": {"type":"VX_icache_stage"}
            }
        },
        "VX_warp_sched": {},
        "VX_icache_stage": {},
        "VX_decode": {},
        "VX_issue": {},
        "VX_execute": {                  
            "submodules": {
                "lsu_unit": {"type":"VX_lsu_unit"},
                "gpu_unit": {"type":"VX_gpu_unit"}
            }
        },
        "VX_commit": {},
        "VX_lsu_unit": {},
        "VX_gpu_unit": {},
        "VX_mem_unit": {
            "submodules": {                
                "dcache": {"type":"VX_cache", "params":{"NUM_BANKS":"`DNUM_BANKS"}},
                "icache": {"type":"VX_cache", "params":{"NUM_BANKS":"`INUM_BANKS"}}
            }
        },
        "VX_cache": {
            "submodules": {
                "bank": {"type":"VX_bank", "count":"NUM_BANKS"}
            }
        },
        "VX_bank": {}
    },
    "taps": {     
        "afu": {                                     
            "!cmd_type":3,
            "!state":3,
            "?cci_sRxPort_c0_mmioRdValid":1,
            "?cci_sRxPort_c0_mmioWrValid":1,
            "mmio_hdr_address":16,            
            "mmio_hdr_length":2,
            "cci_sRxPort_c0_hdr_mdata":16,            
            "?cci_sRxPort_c0_rspValid":1,
            "?cci_sRxPort_c1_rspValid":1,            
            "?cci_sTxPort_c0_valid":1,
            "cci_sTxPort_c0_hdr_address":42,
            "cci_sTxPort_c0_hdr_mdata":16,
            "?cci_sTxPort_c1_valid":1,            
            "cci_sTxPort_c1_hdr_address":42,            
            "cci_sTxPort_c2_mmioRdValid":1,            
            "!cci_sRxPort_c0TxAlmFull":1,
            "!cci_sRxPort_c1TxAlmFull":1,
            "avs_address":26,
            "!avs_waitrequest":1,
            "?avs_write_fire":1,
            "?avs_read_fire":1,
            "avs_byteenable":64,
            "avs_burstcount":4,
            "avs_readdatavalid":1,
            "mem_bank_select":1,
            "cci_dram_rd_req_ctr":26,
            "cci_dram_wr_req_ctr":26,
            "cci_rd_req_ctr":26,
            "cci_rd_rsp_ctr":3,
            "cci_wr_req_ctr":26,
            "?cci_wr_req_fire":1,
            "?cci_wr_rsp_fire":1,
            "?cci_rd_req_fire":1,
            "?cci_rd_rsp_fire":1,
            "!cci_pending_reads_full":1,
            "!cci_pending_writes_empty":1,
            "!cci_pending_writes_full": 1,
            "?afu_dram_req_fire": 1,            
            "afu_dram_req_addr": 26,
            "afu_dram_req_tag": 28,
            "?afu_dram_rsp_fire": 1,
            "afu_dram_rsp_tag": 28
        },
        "afu/vortex": {
            "!reset": 1,
            "?dram_req_fire": 1,
            "dram_req_addr": 32,
            "dram_req_rw": 1,
            "dram_req_byteen":"`VX_DRAM_BYTEEN_WIDTH",
            "dram_req_data":"`VX_DRAM_LINE_WIDTH",
            "dram_req_tag":"`VX_DRAM_TAG_WIDTH",
            "?dram_rsp_fire": 1,
            "dram_rsp_data":"`VX_DRAM_LINE_WIDTH",
            "dram_rsp_tag":"`VX_DRAM_TAG_WIDTH",
            "busy": 1       
        },
        "afu/vortex/cluster/core/pipeline/fetch/icache_stage": {
            "?icache_req_fire": 1,            
            "icache_req_wid":"`NW_BITS",
            "icache_req_addr": 32,
            "icache_req_tag":"`ICORE_TAG_ID_BITS",
            "?icache_rsp_fire": 1,
            "icache_rsp_data": 32,
            "icache_rsp_tag":"`ICORE_TAG_ID_BITS"
        },
        "afu/vortex/cluster/core/pipeline/fetch/warp_sched": {
            "?wsched_scheduled_warp": 1,
            "wsched_active_warps": "`NUM_WARPS",
            "wsched_schedule_table": "`NUM_WARPS",
            "wsched_schedule_ready": "`NUM_WARPS",
            "wsched_warp_to_schedule": "`NW_BITS",
            "wsched_warp_pc": "32"
        },
        "afu/vortex/cluster/core/pipeline/execute/gpu_unit": {
            "?gpu_rsp_valid": 1, 
            "gpu_rsp_wid": "`NW_BITS", 
            "gpu_rsp_tmc": "`GPU_TMC_SIZE", 
            "gpu_rsp_wspawn": "`GPU_WSPAWN_SIZE",             
            "gpu_rsp_split": "`GPU_SPLIT_SIZE",
            "gpu_rsp_barrier": "`GPU_BARRIER_SIZE"
        },
        "afu/vortex/cluster/core/pipeline/execute/lsu_unit": {
            "?dcache_req_fire":"`NUM_THREADS",
            "dcache_req_wid":"`NW_BITS",
            "dcache_req_pc": 32,
            "dcache_req_addr":"`NUM_THREADS * 32",
            "dcache_req_rw": 1,
            "dcache_req_byteen":"`NUM_THREADS * 4",
            "dcache_req_data":  "`NUM_THREADS * 32",
            "dcache_req_tag":"`DCORE_TAG_ID_BITS",  
            "?dcache_rsp_fire":"`NUM_THREADS",
            "dcache_rsp_data":"`NUM_THREADS * 32",
            "dcache_rsp_tag":"`DCORE_TAG_ID_BITS"
        },
        "afu/vortex/cluster/core/pipeline/issue": {
            "?issue_fire": 1,
            "issue_wid":"`NW_BITS",
            "issue_tmask":"`NUM_THREADS",
            "issue_pc": 32,
            "issue_ex_type":"`EX_BITS",
            "issue_op_type":"`OP_BITS",
            "issue_op_mod":"`MOD_BITS",
            "issue_wb": 1,
            "issue_rd":"`NR_BITS",
            "issue_rs1":"`NR_BITS",
            "issue_rs2":"`NR_BITS",
            "issue_rs3":"`NR_BITS",
            "issue_imm": 32,
            "issue_use_pc": 1,
            "issue_use_imm": 1,
            "gpr_rsp_a":"`NUM_THREADS * 32",
            "gpr_rsp_b":"`NUM_THREADS * 32",
            "gpr_rsp_c":"`NUM_THREADS * 32",
            "?writeback_valid": 1,
            "writeback_wid":"`NW_BITS",
            "writeback_pc": 32,
            "writeback_tmask":"`NUM_THREADS",
            "writeback_rd":"`NR_BITS",
            "writeback_data":"`NUM_THREADS * 32",
            "writeback_eop": 1,
            "!scoreboard_delay": 1,        
            "!execute_delay": 1
        },   
        "afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank": {
            "?valid_st0": 1,
            "?valid_st1": 1,
            "addr_st0": 32,
            "addr_st1": 32,
            "is_fill_st0": 1,
            "is_mshr_st0": 1,
            "miss_st0": 1,
            "force_miss_st0": 1, 
            "mshr_push": 1,
            "?crsq_in_stall": 1,
            "?dreq_alm_full": 1,
            "?mshr_alm_full": 1
        }
    }
 }
 