From 00a5122fd402836f5090176fc3ba2a2b8c907454 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 23 Apr 2020 13:49:45 -0400 Subject: [PATCH] RTL code refactoring --- hw/rtl/VX_dmem_ctrl.v | 164 +++++++++--------- hw/rtl/Vortex.v | 108 ++++++------ hw/rtl/Vortex_Socket.v | 1 - ...snp_req_rsp_if.v => VX_cache_snp_req_if.v} | 10 +- 4 files changed, 138 insertions(+), 145 deletions(-) rename hw/rtl/interfaces/{VX_cache_snp_req_rsp_if.v => VX_cache_snp_req_if.v} (50%) diff --git a/hw/rtl/VX_dmem_ctrl.v b/hw/rtl/VX_dmem_ctrl.v index 331a527e..11e1c225 100644 --- a/hw/rtl/VX_dmem_ctrl.v +++ b/hw/rtl/VX_dmem_ctrl.v @@ -1,26 +1,26 @@ `include "VX_define.vh" module VX_dmem_ctrl ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, // Dram <-> Dcache - VX_cache_dram_req_if cache_dram_req_if, - VX_cache_dram_rsp_if cache_dram_rsp_if, - VX_cache_snp_req_rsp_if gpu_dcache_snp_req_if, + VX_cache_dram_req_if cache_dram_req_if, + VX_cache_dram_rsp_if cache_dram_rsp_if, + VX_cache_snp_req_if dcache_snp_req_if, // Dram <-> Icache - VX_cache_dram_req_if gpu_icache_dram_req_if, - VX_cache_dram_rsp_if gpu_icache_dram_rsp_if, - VX_cache_snp_req_rsp_if gpu_icache_snp_req_if, + VX_cache_dram_req_if icache_dram_req_if, + VX_cache_dram_rsp_if icache_dram_rsp_if, + VX_cache_snp_req_if icache_snp_req_if, // Core <-> Dcache - VX_cache_core_rsp_if dcache_rsp_if, - VX_cache_core_req_if dcache_req_if, + VX_cache_core_rsp_if dcache_core_rsp_if, + VX_cache_core_req_if dcache_core_req_if, // Core <-> Icache - VX_cache_core_rsp_if icache_rsp_if, - VX_cache_core_req_if icache_req_if + VX_cache_core_rsp_if icache_core_rsp_if, + VX_cache_core_req_if icache_core_req_if ); VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_smem_if(); @@ -29,47 +29,47 @@ module VX_dmem_ctrl ( VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_dcache_if(); VX_cache_core_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_rsp_dcache_if(); - wire to_shm = dcache_req_if.core_req_addr[0][31:24] == 8'hFF; + wire to_shm = dcache_core_req_if.core_req_addr[0][31:24] == 8'hFF; wire dcache_wants_wb = (|dcache_rsp_dcache_if.core_rsp_valid); // Dcache Request - assign dcache_req_dcache_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{~to_shm}}; - assign dcache_req_dcache_if.core_req_read = dcache_req_if.core_req_read; - assign dcache_req_dcache_if.core_req_write = dcache_req_if.core_req_write; - assign dcache_req_dcache_if.core_req_addr = dcache_req_if.core_req_addr; - assign dcache_req_dcache_if.core_req_data = dcache_req_if.core_req_data; - assign dcache_req_dcache_if.core_req_rd = dcache_req_if.core_req_rd; - assign dcache_req_dcache_if.core_req_wb = dcache_req_if.core_req_wb; - assign dcache_req_dcache_if.core_req_warp_num = dcache_req_if.core_req_warp_num; - assign dcache_req_dcache_if.core_req_pc = dcache_req_if.core_req_pc; + assign dcache_req_dcache_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{~to_shm}}; + assign dcache_req_dcache_if.core_req_read = dcache_core_req_if.core_req_read; + assign dcache_req_dcache_if.core_req_write = dcache_core_req_if.core_req_write; + assign dcache_req_dcache_if.core_req_addr = dcache_core_req_if.core_req_addr; + assign dcache_req_dcache_if.core_req_data = dcache_core_req_if.core_req_data; + assign dcache_req_dcache_if.core_req_rd = dcache_core_req_if.core_req_rd; + assign dcache_req_dcache_if.core_req_wb = dcache_core_req_if.core_req_wb; + assign dcache_req_dcache_if.core_req_warp_num = dcache_core_req_if.core_req_warp_num; + assign dcache_req_dcache_if.core_req_pc = dcache_core_req_if.core_req_pc; - assign dcache_rsp_dcache_if.core_rsp_ready = dcache_rsp_if.core_rsp_ready; + assign dcache_rsp_dcache_if.core_rsp_ready = dcache_core_rsp_if.core_rsp_ready; // Shared Memory Request - assign dcache_req_smem_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{to_shm}}; - assign dcache_req_smem_if.core_req_addr = dcache_req_if.core_req_addr; - assign dcache_req_smem_if.core_req_data = dcache_req_if.core_req_data; - assign dcache_req_smem_if.core_req_read = dcache_req_if.core_req_read; - assign dcache_req_smem_if.core_req_write = dcache_req_if.core_req_write; - assign dcache_req_smem_if.core_req_rd = dcache_req_if.core_req_rd; - assign dcache_req_smem_if.core_req_wb = dcache_req_if.core_req_wb; - assign dcache_req_smem_if.core_req_warp_num = dcache_req_if.core_req_warp_num; - assign dcache_req_smem_if.core_req_pc = dcache_req_if.core_req_pc; + assign dcache_req_smem_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{to_shm}}; + assign dcache_req_smem_if.core_req_addr = dcache_core_req_if.core_req_addr; + assign dcache_req_smem_if.core_req_data = dcache_core_req_if.core_req_data; + assign dcache_req_smem_if.core_req_read = dcache_core_req_if.core_req_read; + assign dcache_req_smem_if.core_req_write = dcache_core_req_if.core_req_write; + assign dcache_req_smem_if.core_req_rd = dcache_core_req_if.core_req_rd; + assign dcache_req_smem_if.core_req_wb = dcache_core_req_if.core_req_wb; + assign dcache_req_smem_if.core_req_warp_num = dcache_core_req_if.core_req_warp_num; + assign dcache_req_smem_if.core_req_pc = dcache_core_req_if.core_req_pc; - assign dcache_rsp_smem_if.core_rsp_ready = dcache_rsp_if.core_rsp_ready && ~dcache_wants_wb; + assign dcache_rsp_smem_if.core_rsp_ready = dcache_core_rsp_if.core_rsp_ready && ~dcache_wants_wb; // Dcache Response - assign dcache_rsp_if.core_rsp_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_valid : dcache_rsp_smem_if.core_rsp_valid; - assign dcache_rsp_if.core_rsp_read = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_read : dcache_rsp_smem_if.core_rsp_read; - assign dcache_rsp_if.core_rsp_write = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_write : dcache_rsp_smem_if.core_rsp_write; - assign dcache_rsp_if.core_rsp_pc = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_pc : dcache_rsp_smem_if.core_rsp_pc; - assign dcache_rsp_if.core_rsp_data = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_data : dcache_rsp_smem_if.core_rsp_data; - assign dcache_rsp_if.core_rsp_warp_num = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_warp_num : dcache_rsp_smem_if.core_rsp_warp_num; + assign dcache_core_rsp_if.core_rsp_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_valid : dcache_rsp_smem_if.core_rsp_valid; + assign dcache_core_rsp_if.core_rsp_read = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_read : dcache_rsp_smem_if.core_rsp_read; + assign dcache_core_rsp_if.core_rsp_write = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_write : dcache_rsp_smem_if.core_rsp_write; + assign dcache_core_rsp_if.core_rsp_pc = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_pc : dcache_rsp_smem_if.core_rsp_pc; + assign dcache_core_rsp_if.core_rsp_data = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_data : dcache_rsp_smem_if.core_rsp_data; + assign dcache_core_rsp_if.core_rsp_warp_num = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_warp_num : dcache_rsp_smem_if.core_rsp_warp_num; - assign dcache_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready; + assign dcache_core_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready; - VX_cache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_req_if(); - VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_rsp_if(); + VX_cache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) smem_dram_req_if(); + VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) smem_dram_rsp_if(); VX_cache #( .CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES), @@ -125,18 +125,18 @@ module VX_dmem_ctrl ( `IGNORE_WARNINGS_END // DRAM response - .dram_rsp_valid (gpu_smem_dram_rsp_if.dram_rsp_valid), - .dram_rsp_addr (gpu_smem_dram_rsp_if.dram_rsp_addr), - .dram_rsp_data (gpu_smem_dram_rsp_if.dram_rsp_data), + .dram_rsp_valid (smem_dram_rsp_if.dram_rsp_valid), + .dram_rsp_addr (smem_dram_rsp_if.dram_rsp_addr), + .dram_rsp_data (smem_dram_rsp_if.dram_rsp_data), // DRAM accept response - .dram_rsp_ready (gpu_smem_dram_req_if.dram_rsp_ready), + .dram_rsp_ready (smem_dram_req_if.dram_rsp_ready), // DRAM Req - .dram_req_read (gpu_smem_dram_req_if.dram_req_read), - .dram_req_write (gpu_smem_dram_req_if.dram_req_write), - .dram_req_addr (gpu_smem_dram_req_if.dram_req_addr), - .dram_req_data (gpu_smem_dram_req_if.dram_req_data), + .dram_req_read (smem_dram_req_if.dram_req_read), + .dram_req_write (smem_dram_req_if.dram_req_write), + .dram_req_addr (smem_dram_req_if.dram_req_addr), + .dram_req_data (smem_dram_req_if.dram_req_data), .dram_req_ready (0), // Snoop Request @@ -223,9 +223,9 @@ module VX_dmem_ctrl ( .dram_req_ready (cache_dram_req_if.dram_req_ready), // Snoop Request - .snp_req_valid (gpu_dcache_snp_req_if.snp_req_valid), - .snp_req_addr (gpu_dcache_snp_req_if.snp_req_addr), - .snp_req_ready (gpu_dcache_snp_req_if.snp_req_ready), + .snp_req_valid (dcache_snp_req_if.snp_req_valid), + .snp_req_addr (dcache_snp_req_if.snp_req_addr), + .snp_req_ready (dcache_snp_req_if.snp_req_ready), // Snoop Forward `IGNORE_WARNINGS_BEGIN @@ -261,52 +261,52 @@ module VX_dmem_ctrl ( .reset (reset), // Core req - .core_req_valid (icache_req_if.core_req_valid), - .core_req_read (icache_req_if.core_req_read), - .core_req_write (icache_req_if.core_req_write), - .core_req_addr (icache_req_if.core_req_addr), - .core_req_data (icache_req_if.core_req_data), - .core_req_rd (icache_req_if.core_req_rd), - .core_req_wb (icache_req_if.core_req_wb), - .core_req_warp_num (icache_req_if.core_req_warp_num), - .core_req_pc (icache_req_if.core_req_pc), + .core_req_valid (icache_core_req_if.core_req_valid), + .core_req_read (icache_core_req_if.core_req_read), + .core_req_write (icache_core_req_if.core_req_write), + .core_req_addr (icache_core_req_if.core_req_addr), + .core_req_data (icache_core_req_if.core_req_data), + .core_req_rd (icache_core_req_if.core_req_rd), + .core_req_wb (icache_core_req_if.core_req_wb), + .core_req_warp_num (icache_core_req_if.core_req_warp_num), + .core_req_pc (icache_core_req_if.core_req_pc), // Can submit core Req - .core_req_ready (icache_req_if.core_req_ready), + .core_req_ready (icache_core_req_if.core_req_ready), // Core Cache Can't WB - .core_rsp_ready (icache_rsp_if.core_rsp_ready), + .core_rsp_ready (icache_core_rsp_if.core_rsp_ready), // Cache CWB - .core_rsp_valid (icache_rsp_if.core_rsp_valid), - .core_rsp_read (icache_rsp_if.core_rsp_read), - .core_rsp_write (icache_rsp_if.core_rsp_write), - .core_rsp_warp_num (icache_rsp_if.core_rsp_warp_num), - .core_rsp_data (icache_rsp_if.core_rsp_data), - .core_rsp_pc (icache_rsp_if.core_rsp_pc), + .core_rsp_valid (icache_core_rsp_if.core_rsp_valid), + .core_rsp_read (icache_core_rsp_if.core_rsp_read), + .core_rsp_write (icache_core_rsp_if.core_rsp_write), + .core_rsp_warp_num (icache_core_rsp_if.core_rsp_warp_num), + .core_rsp_data (icache_core_rsp_if.core_rsp_data), + .core_rsp_pc (icache_core_rsp_if.core_rsp_pc), `IGNORE_WARNINGS_BEGIN .core_rsp_addr (), `IGNORE_WARNINGS_END // DRAM response - .dram_rsp_valid (gpu_icache_dram_rsp_if.dram_rsp_valid), - .dram_rsp_addr (gpu_icache_dram_rsp_if.dram_rsp_addr), - .dram_rsp_data (gpu_icache_dram_rsp_if.dram_rsp_data), + .dram_rsp_valid (icache_dram_rsp_if.dram_rsp_valid), + .dram_rsp_addr (icache_dram_rsp_if.dram_rsp_addr), + .dram_rsp_data (icache_dram_rsp_if.dram_rsp_data), // DRAM accept response - .dram_rsp_ready (gpu_icache_dram_req_if.dram_rsp_ready), + .dram_rsp_ready (icache_dram_req_if.dram_rsp_ready), // DRAM Req - .dram_req_read (gpu_icache_dram_req_if.dram_req_read), - .dram_req_write (gpu_icache_dram_req_if.dram_req_write), - .dram_req_addr (gpu_icache_dram_req_if.dram_req_addr), - .dram_req_data (gpu_icache_dram_req_if.dram_req_data), - .dram_req_ready (gpu_icache_dram_req_if.dram_req_ready), + .dram_req_read (icache_dram_req_if.dram_req_read), + .dram_req_write (icache_dram_req_if.dram_req_write), + .dram_req_addr (icache_dram_req_if.dram_req_addr), + .dram_req_data (icache_dram_req_if.dram_req_data), + .dram_req_ready (icache_dram_req_if.dram_req_ready), // Snoop Request - .snp_req_valid (gpu_icache_snp_req_if.snp_req_valid), - .snp_req_addr (gpu_icache_snp_req_if.snp_req_addr), - .snp_req_ready (gpu_icache_snp_req_if.snp_req_ready), + .snp_req_valid (icache_snp_req_if.snp_req_valid), + .snp_req_addr (icache_snp_req_if.snp_req_addr), + .snp_req_ready (icache_snp_req_if.snp_req_ready), // Snoop Forward `IGNORE_WARNINGS_BEGIN diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index df974977..9b082ccf 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -43,14 +43,12 @@ module Vortex #( input wire [31:0] llc_snp_req_addr, output wire llc_snp_req_ready, - // CSR request //input wire csr_read_valid; //input wire csr_write_valid; //input wire [`CSR_WIDTH-1:0 csr_index; //input wire csr_data_in; - //output wire [15:0] csr_data_out; - + //output wire [15:0] csr_data_out; output wire ebreak ); @@ -64,9 +62,9 @@ module Vortex #( wire schedule_delay; // Dcache Interface - VX_cache_core_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_rsp_if(); - VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_if(); - VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_qual_if(); + VX_cache_core_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_rsp_if(); + VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_req_if(); + VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_req_qual_if(); VX_cache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) cache_dram_req_if(); VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) cache_dram_rsp_if(); @@ -85,53 +83,53 @@ module Vortex #( generate for (i = 0; i < `DBANK_LINE_WORDS; i=i+1) begin assign cache_dram_rsp_if.dram_rsp_data[i] = dram_rsp_data[i * 32 +: 32]; - assign dram_req_data[i * 32 +: 32] = cache_dram_req_if.dram_req_data[i]; + assign dram_req_data[i * 32 +: 32] = cache_dram_req_if.dram_req_data[i]; end endgenerate wire temp_io_valid = (!memory_delay) - && (|dcache_req_if.core_req_valid) - && (dcache_req_if.core_req_write[0] != `NO_MEM_WRITE) - && (dcache_req_if.core_req_addr[0] == `IO_BUS_ADDR); + && (|dcache_core_req_if.core_req_valid) + && (dcache_core_req_if.core_req_write[0] != `NO_MEM_WRITE) + && (dcache_core_req_if.core_req_addr[0] == `IO_BUS_ADDR); - wire [31:0] temp_io_data = dcache_req_if.core_req_data[0]; + wire [31:0] temp_io_data = dcache_core_req_if.core_req_data[0]; assign io_valid = temp_io_valid; assign io_data = temp_io_data; - assign dcache_req_qual_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{~io_valid}}; - assign dcache_req_qual_if.core_req_read = dcache_req_if.core_req_read; - assign dcache_req_qual_if.core_req_write = dcache_req_if.core_req_write; - assign dcache_req_qual_if.core_req_addr = dcache_req_if.core_req_addr; - assign dcache_req_qual_if.core_req_data = dcache_req_if.core_req_data; + assign dcache_core_req_qual_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{~io_valid}}; + assign dcache_core_req_qual_if.core_req_read = dcache_core_req_if.core_req_read; + assign dcache_core_req_qual_if.core_req_write = dcache_core_req_if.core_req_write; + assign dcache_core_req_qual_if.core_req_addr = dcache_core_req_if.core_req_addr; + assign dcache_core_req_qual_if.core_req_data = dcache_core_req_if.core_req_data; - assign dcache_req_if.core_req_ready = dcache_req_qual_if.core_req_ready; + assign dcache_core_req_if.core_req_ready = dcache_core_req_qual_if.core_req_ready; - assign dcache_req_qual_if.core_req_rd = dcache_req_if.core_req_rd; - assign dcache_req_qual_if.core_req_wb = dcache_req_if.core_req_wb; - assign dcache_req_qual_if.core_req_warp_num = dcache_req_if.core_req_warp_num; - assign dcache_req_qual_if.core_req_pc = dcache_req_if.core_req_pc; + assign dcache_core_req_qual_if.core_req_rd = dcache_core_req_if.core_req_rd; + assign dcache_core_req_qual_if.core_req_wb = dcache_core_req_if.core_req_wb; + assign dcache_core_req_qual_if.core_req_warp_num = dcache_core_req_if.core_req_warp_num; + assign dcache_core_req_qual_if.core_req_pc = dcache_core_req_if.core_req_pc; - VX_cache_core_rsp_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_rsp_if(); - VX_cache_core_req_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_req_if(); + VX_cache_core_rsp_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_core_rsp_if(); + VX_cache_core_req_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_core_req_if(); - VX_cache_dram_req_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) gpu_icache_dram_req_if(); - VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) gpu_icache_dram_rsp_if(); + VX_cache_dram_req_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) icache_dram_req_if(); + VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) icache_dram_rsp_if(); - assign gpu_icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid; - assign gpu_icache_dram_rsp_if.dram_rsp_addr = I_dram_rsp_addr; + assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid; + assign icache_dram_rsp_if.dram_rsp_addr = I_dram_rsp_addr; - assign I_dram_req_write = gpu_icache_dram_req_if.dram_req_write; - assign I_dram_req_read = gpu_icache_dram_req_if.dram_req_read; - assign I_dram_req_addr = gpu_icache_dram_req_if.dram_req_addr; - assign I_dram_rsp_ready = gpu_icache_dram_req_if.dram_rsp_ready; + assign I_dram_req_write = icache_dram_req_if.dram_req_write; + assign I_dram_req_read = icache_dram_req_if.dram_req_read; + assign I_dram_req_addr = icache_dram_req_if.dram_req_addr; + assign I_dram_rsp_ready = icache_dram_req_if.dram_rsp_ready; - assign gpu_icache_dram_req_if.dram_req_ready = I_dram_req_ready; + assign icache_dram_req_if.dram_req_ready = I_dram_req_ready; genvar j; generate for (j = 0; j < `IBANK_LINE_WORDS; j = j + 1) begin - assign gpu_icache_dram_rsp_if.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32]; - assign I_dram_req_data[j * 32 +: 32] = gpu_icache_dram_req_if.dram_req_data[j]; + assign icache_dram_rsp_if.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32]; + assign I_dram_req_data[j * 32 +: 32] = icache_dram_req_if.dram_req_data[j]; end endgenerate @@ -149,11 +147,11 @@ VX_jal_rsp_if jal_rsp_if(); // Jump resolution to Fetch VX_warp_ctl_if warp_ctl_if(); // Cache snooping -VX_cache_snp_req_rsp_if gpu_icache_snp_req_if(); -VX_cache_snp_req_rsp_if gpu_dcache_snp_req_if(); -assign gpu_dcache_snp_req_if.snp_req_valid = llc_snp_req_valid; -assign gpu_dcache_snp_req_if.snp_req_addr = llc_snp_req_addr; -assign llc_snp_req_ready = gpu_dcache_snp_req_if.snp_req_ready; +VX_cache_snp_req_if icache_snp_req_if(); +VX_cache_snp_req_if dcache_snp_req_if(); +assign dcache_snp_req_if.snp_req_valid = llc_snp_req_valid; +assign dcache_snp_req_if.snp_req_addr = llc_snp_req_addr; +assign llc_snp_req_ready = dcache_snp_req_if.snp_req_ready; VX_front_end front_end ( .clk (clk), @@ -161,8 +159,8 @@ VX_front_end front_end ( .warp_ctl_if (warp_ctl_if), .bckE_req_if (bckE_req_if), .schedule_delay (schedule_delay), - .icache_rsp_if (icache_rsp_if), - .icache_req_if (icache_req_if), + .icache_rsp_if (icache_core_rsp_if), + .icache_req_if (icache_core_req_if), .jal_rsp_if (jal_rsp_if), .branch_rsp_if (branch_rsp_if), .fetch_ebreak (ebreak) @@ -190,8 +188,8 @@ VX_back_end #( .bckE_req_if (bckE_req_if), .jal_rsp_if (jal_rsp_if), .branch_rsp_if (branch_rsp_if), - .dcache_rsp_if (dcache_rsp_if), - .dcache_req_if (dcache_req_if), + .dcache_rsp_if (dcache_core_rsp_if), + .dcache_req_if (dcache_core_req_if), .writeback_if (writeback_if), .mem_delay (memory_delay), .exec_delay (exec_delay), @@ -199,26 +197,26 @@ VX_back_end #( ); VX_dmem_ctrl dmem_ctrl ( - .clk (clk), - .reset (reset), + .clk (clk), + .reset (reset), // Dram <-> Dcache - .cache_dram_req_if (cache_dram_req_if), - .cache_dram_rsp_if (cache_dram_rsp_if), - .gpu_dcache_snp_req_if (gpu_dcache_snp_req_if), + .cache_dram_req_if (cache_dram_req_if), + .cache_dram_rsp_if (cache_dram_rsp_if), + .dcache_snp_req_if (dcache_snp_req_if), // Dram <-> Icache - .gpu_icache_dram_req_if (gpu_icache_dram_req_if), - .gpu_icache_dram_rsp_if (gpu_icache_dram_rsp_if), - .gpu_icache_snp_req_if (gpu_icache_snp_req_if), + .icache_dram_req_if (icache_dram_req_if), + .icache_dram_rsp_if (icache_dram_rsp_if), + .icache_snp_req_if (icache_snp_req_if), // Core <-> Icache - .icache_req_if (icache_req_if), - .icache_rsp_if (icache_rsp_if), + .icache_core_req_if (icache_core_req_if), + .icache_core_rsp_if (icache_core_rsp_if), // Core <-> Dcache - .dcache_req_if (dcache_req_qual_if), - .dcache_rsp_if (dcache_rsp_if) + .dcache_core_req_if (dcache_core_req_qual_if), + .dcache_core_rsp_if (dcache_core_rsp_if) ); endmodule // Vortex diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index 1e9e66e7..22f6aee4 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -35,7 +35,6 @@ module Vortex_Socket ( wire[`NUM_CORES-1:0] cluster_io_valid; wire[`NUM_CORES-1:0][31:0] cluster_io_data; - genvar curr_c; for (curr_c = 0; curr_c < `NUM_CORES; curr_c=curr_c+1) begin assign io_valid[curr_c] = cluster_io_valid[curr_c]; diff --git a/hw/rtl/interfaces/VX_cache_snp_req_rsp_if.v b/hw/rtl/interfaces/VX_cache_snp_req_if.v similarity index 50% rename from hw/rtl/interfaces/VX_cache_snp_req_rsp_if.v rename to hw/rtl/interfaces/VX_cache_snp_req_if.v index b937ca0d..d9fc7ed1 100644 --- a/hw/rtl/interfaces/VX_cache_snp_req_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_snp_req_if.v @@ -1,18 +1,14 @@ -`ifndef VX_CACHE_SNP_REQ_RSP_IF -`define VX_CACHE_SNP_REQ_RSP_IF +`ifndef VX_CACHE_SNP_REQ_IF +`define VX_CACHE_SNP_REQ_IF `include "../cache/VX_cache_config.vh" -interface VX_cache_snp_req_rsp_if (); +interface VX_cache_snp_req_if (); - // Snoop request wire snp_req_valid; wire [31:0] snp_req_addr; wire snp_req_ready; - // Snoop Response - // TODO: - endinterface `endif \ No newline at end of file