code refactoring for Vivado compatibility
This commit is contained in:
Blaise Tine
254
hw/rtl/VX_issue.sv
Normal file
254
hw/rtl/VX_issue.sv
Normal file
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`include "VX_define.vh"
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module VX_issue #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_issue
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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VX_perf_pipeline_if.master perf_pipeline_if,
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`endif
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VX_decode_if.slave decode_if,
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VX_writeback_if.slave writeback_if,
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VX_alu_req_if.master alu_req_if,
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VX_lsu_req_if.master lsu_req_if,
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VX_csr_req_if.master csr_req_if,
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`ifdef EXT_F_ENABLE
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VX_fpu_req_if.master fpu_req_if,
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`endif
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VX_gpu_req_if.master gpu_req_if
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);
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VX_ibuffer_if ibuffer_if();
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VX_gpr_rsp_if gpr_rsp_if();
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VX_gpr_req_if gpr_req_if();
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assign gpr_req_if.wid = ibuffer_if.wid;
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assign gpr_req_if.rs1 = ibuffer_if.rs1;
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assign gpr_req_if.rs2 = ibuffer_if.rs2;
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assign gpr_req_if.rs3 = ibuffer_if.rs3;
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VX_writeback_if sboard_wb_if();
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assign sboard_wb_if.valid = writeback_if.valid;
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assign sboard_wb_if.wid = writeback_if.wid;
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assign sboard_wb_if.PC = writeback_if.PC;
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assign sboard_wb_if.rd = writeback_if.rd;
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assign sboard_wb_if.eop = writeback_if.eop;
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assign sboard_wb_if.ready = writeback_if.ready;
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VX_ibuffer_if sboard_ib_if();
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assign sboard_ib_if.valid = ibuffer_if.valid && idmux_ib_if.ready;
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assign sboard_ib_if.wid = ibuffer_if.wid;
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assign sboard_ib_if.PC = ibuffer_if.PC;
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assign sboard_ib_if.wb = ibuffer_if.wb;
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assign sboard_ib_if.rd = ibuffer_if.rd;
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assign sboard_ib_if.rd_n = ibuffer_if.rd_n;
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assign sboard_ib_if.rs1_n = ibuffer_if.rs1_n;
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assign sboard_ib_if.rs2_n = ibuffer_if.rs2_n;
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assign sboard_ib_if.rs3_n = ibuffer_if.rs3_n;
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assign sboard_ib_if.wid_n = ibuffer_if.wid_n;
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VX_ibuffer_if idmux_ib_if();
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assign idmux_ib_if.valid = ibuffer_if.valid && sboard_ib_if.ready;
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assign idmux_ib_if.wid = ibuffer_if.wid;
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assign idmux_ib_if.tmask = ibuffer_if.tmask;
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assign idmux_ib_if.PC = ibuffer_if.PC;
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assign idmux_ib_if.ex_type = ibuffer_if.ex_type;
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assign idmux_ib_if.op_type = ibuffer_if.op_type;
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assign idmux_ib_if.op_mod = ibuffer_if.op_mod;
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assign idmux_ib_if.wb = ibuffer_if.wb;
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assign idmux_ib_if.rd = ibuffer_if.rd;
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assign idmux_ib_if.rs1 = ibuffer_if.rs1;
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assign idmux_ib_if.imm = ibuffer_if.imm;
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assign idmux_ib_if.use_PC = ibuffer_if.use_PC;
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assign idmux_ib_if.use_imm = ibuffer_if.use_imm;
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// issue the instruction
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assign ibuffer_if.ready = sboard_ib_if.ready && idmux_ib_if.ready;
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`RESET_RELAY (ibuf_reset);
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`RESET_RELAY (gpr_reset);
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`RESET_RELAY (demux_reset);
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VX_ibuffer #(
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.CORE_ID(CORE_ID)
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) ibuffer (
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.clk (clk),
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.reset (ibuf_reset),
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.decode_if (decode_if),
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.ibuffer_if (ibuffer_if)
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);
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VX_scoreboard #(
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.CORE_ID(CORE_ID)
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) scoreboard (
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.clk (clk),
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.reset (reset),
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.ibuffer_if (sboard_ib_if),
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.writeback_if(sboard_wb_if)
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);
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VX_gpr_stage #(
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.CORE_ID(CORE_ID)
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) gpr_stage (
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.clk (clk),
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.reset (gpr_reset),
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.writeback_if (writeback_if),
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.gpr_req_if (gpr_req_if),
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.gpr_rsp_if (gpr_rsp_if)
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);
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VX_instr_demux instr_demux (
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.clk (clk),
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.reset (demux_reset),
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.ibuffer_if (idmux_ib_if),
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.gpr_rsp_if (gpr_rsp_if),
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.alu_req_if (alu_req_if),
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.lsu_req_if (lsu_req_if),
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.csr_req_if (csr_req_if),
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`ifdef EXT_F_ENABLE
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.fpu_req_if (fpu_req_if),
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`endif
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.gpu_req_if (gpu_req_if)
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);
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`SCOPE_ASSIGN (issue_fire, ibuffer_if.valid && ibuffer_if.ready);
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`SCOPE_ASSIGN (issue_wid, ibuffer_if.wid);
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`SCOPE_ASSIGN (issue_tmask, ibuffer_if.tmask);
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`SCOPE_ASSIGN (issue_pc, ibuffer_if.PC);
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`SCOPE_ASSIGN (issue_ex_type, ibuffer_if.ex_type);
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`SCOPE_ASSIGN (issue_op_type, ibuffer_if.op_type);
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`SCOPE_ASSIGN (issue_op_mod, ibuffer_if.op_mod);
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`SCOPE_ASSIGN (issue_wb, ibuffer_if.wb);
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`SCOPE_ASSIGN (issue_rd, ibuffer_if.rd);
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`SCOPE_ASSIGN (issue_rs1, ibuffer_if.rs1);
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`SCOPE_ASSIGN (issue_rs2, ibuffer_if.rs2);
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`SCOPE_ASSIGN (issue_rs3, ibuffer_if.rs3);
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`SCOPE_ASSIGN (issue_imm, ibuffer_if.imm);
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`SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC);
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`SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm);
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`SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay);
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`SCOPE_ASSIGN (execute_delay, ~idmux_ib_if.ready);
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`SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data);
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`SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data);
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`SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data);
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`SCOPE_ASSIGN (writeback_valid, writeback_if.valid);
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`SCOPE_ASSIGN (writeback_tmask, writeback_if.tmask);
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`SCOPE_ASSIGN (writeback_wid, writeback_if.wid);
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`SCOPE_ASSIGN (writeback_pc, writeback_if.PC);
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`SCOPE_ASSIGN (writeback_rd, writeback_if.rd);
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`SCOPE_ASSIGN (writeback_data, writeback_if.data);
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`SCOPE_ASSIGN (writeback_eop, writeback_if.eop);
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`ifdef PERF_ENABLE
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reg [`PERF_CTR_BITS-1:0] perf_ibf_stalls;
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reg [`PERF_CTR_BITS-1:0] perf_scb_stalls;
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reg [`PERF_CTR_BITS-1:0] perf_alu_stalls;
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reg [`PERF_CTR_BITS-1:0] perf_lsu_stalls;
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reg [`PERF_CTR_BITS-1:0] perf_csr_stalls;
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reg [`PERF_CTR_BITS-1:0] perf_gpu_stalls;
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`ifdef EXT_F_ENABLE
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reg [`PERF_CTR_BITS-1:0] perf_fpu_stalls;
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`endif
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always @(posedge clk) begin
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if (reset) begin
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perf_ibf_stalls <= 0;
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perf_scb_stalls <= 0;
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perf_alu_stalls <= 0;
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perf_lsu_stalls <= 0;
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perf_csr_stalls <= 0;
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perf_gpu_stalls <= 0;
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`ifdef EXT_F_ENABLE
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perf_fpu_stalls <= 0;
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`endif
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end else begin
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if (decode_if.valid & !decode_if.ready) begin
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perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1;
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end
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if (ibuffer_if.valid & scoreboard_delay) begin
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perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1;
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end
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if (alu_req_if.valid & !alu_req_if.ready) begin
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perf_alu_stalls <= perf_alu_stalls + `PERF_CTR_BITS'd1;
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end
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if (lsu_req_if.valid & !lsu_req_if.ready) begin
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perf_lsu_stalls <= perf_lsu_stalls + `PERF_CTR_BITS'd1;
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end
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if (csr_req_if.valid & !csr_req_if.ready) begin
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perf_csr_stalls <= perf_csr_stalls + `PERF_CTR_BITS'd1;
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end
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if (gpu_req_if.valid & !gpu_req_if.ready) begin
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perf_gpu_stalls <= perf_gpu_stalls + `PERF_CTR_BITS'd1;
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end
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`ifdef EXT_F_ENABLE
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if (fpu_req_if.valid & !fpu_req_if.ready) begin
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perf_fpu_stalls <= perf_fpu_stalls + `PERF_CTR_BITS'd1;
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end
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`endif
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end
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end
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assign perf_pipeline_if.ibf_stalls = perf_ibf_stalls;
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assign perf_pipeline_if.scb_stalls = perf_scb_stalls;
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assign perf_pipeline_if.alu_stalls = perf_alu_stalls;
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assign perf_pipeline_if.lsu_stalls = perf_lsu_stalls;
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assign perf_pipeline_if.csr_stalls = perf_csr_stalls;
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assign perf_pipeline_if.gpu_stalls = perf_gpu_stalls;
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`ifdef EXT_F_ENABLE
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assign perf_pipeline_if.fpu_stalls = perf_fpu_stalls;
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`endif
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`endif
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (alu_req_if.valid && alu_req_if.ready) begin
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dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=ALU, tmask=%b, rd=%0d, rs1_data=",
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$time, CORE_ID, alu_req_if.wid, alu_req_if.PC, alu_req_if.tmask, alu_req_if.rd);
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`TRACE_ARRAY1D(alu_req_if.rs1_data, `NUM_THREADS);
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dpi_trace(", rs2_data=");
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`TRACE_ARRAY1D(alu_req_if.rs2_data, `NUM_THREADS);
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dpi_trace("\n");
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end
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if (lsu_req_if.valid && lsu_req_if.ready) begin
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dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=LSU, tmask=%b, rd=%0d, offset=%0h, addr=",
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$time, CORE_ID, lsu_req_if.wid, lsu_req_if.PC, lsu_req_if.tmask, lsu_req_if.rd, lsu_req_if.offset);
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`TRACE_ARRAY1D(lsu_req_if.base_addr, `NUM_THREADS);
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dpi_trace(", data=");
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`TRACE_ARRAY1D(lsu_req_if.store_data, `NUM_THREADS);
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dpi_trace("\n");
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end
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if (csr_req_if.valid && csr_req_if.ready) begin
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dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=CSR, tmask=%b, rd=%0d, addr=%0h, rs1_data=",
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$time, CORE_ID, csr_req_if.wid, csr_req_if.PC, csr_req_if.tmask, csr_req_if.rd, csr_req_if.addr);
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`TRACE_ARRAY1D(csr_req_if.rs1_data, `NUM_THREADS);
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dpi_trace("\n");
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end
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`ifdef EXT_F_ENABLE
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if (fpu_req_if.valid && fpu_req_if.ready) begin
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dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=FPU, tmask=%b, rd=%0d, rs1_data=",
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$time, CORE_ID, fpu_req_if.wid, fpu_req_if.PC, fpu_req_if.tmask, fpu_req_if.rd);
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`TRACE_ARRAY1D(fpu_req_if.rs1_data, `NUM_THREADS);
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dpi_trace(", rs2_data=");
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`TRACE_ARRAY1D(fpu_req_if.rs2_data, `NUM_THREADS);
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dpi_trace(", rs3_data=");
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`TRACE_ARRAY1D(fpu_req_if.rs3_data, `NUM_THREADS);
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dpi_trace("\n");
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end
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`endif
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if (gpu_req_if.valid && gpu_req_if.ready) begin
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dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=GPU, tmask=%b, rd=%0d, rs1_data=",
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$time, CORE_ID, gpu_req_if.wid, gpu_req_if.PC, gpu_req_if.tmask, gpu_req_if.rd);
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`TRACE_ARRAY1D(gpu_req_if.rs1_data, `NUM_THREADS);
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dpi_trace(", rs2_data=");
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`TRACE_ARRAY1D(gpu_req_if.rs2_data, `NUM_THREADS);
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dpi_trace("\n");
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end
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end
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`endif
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endmodule
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